Examples of Laboratory Web Page and Processor Visual Simulator

A Pipelined Processor Visual Simulator

Laboratory of Computer Organization and Design

Usage of MAX+PLUS II

MIPS Instructions To Be Implemented in CPU Designs:

MIPS Instructions

Bit # 31..26 25..21 20..16 15..11 10..6 5..0

R-type op rs rt rd sa func

add 000000 rs rt rd 00000 100000 rd <- rs + rt

sub 000000 rs rt rd 00000 100010 rd <- rs - rt

and 000000 rs rt rd 00000 100100 rd <- rs & rt

or 000000 rs rt rd 00000 100101 rd <- rs | rt

sll 000000 00000 rt rd sa 000000 rd <- rt << sa

srl 000000 00000 rt rd sa 000010 rd <- rt >> sa (logical)

sra 000000 00000 rt rd sa 000011 rd <- rt >> sa (arithmetic)

I-type op rs rt immediate

addi 001000 rs rt immediate rt <- rs + (sign-extend)immediate

andi 001100 rs rt immediate rt <- rs & (zero-extend)immediate

ori 001101 rs rt immediate rt <- rs | (zero-extend)immediate

lw 100011 rs rt immediate rt <- memory[rs + (sign-extend)immediate]

sw 101011 rs rt immediate memory[rs + (sign-extend)immediate] <- rt

beq 000100 rs rt immediate if (rs == rt) PC <- PC+4 + (sign-extend)immediate<<2

bne 000101 rs rt immediate if (rs != rt) PC <- PC+4 + (sign-extend)immediate<<2

J-type op address

j 000010 address PC <- (PC+4)[31..28],address,0,0

Basic Components Design: Multiplexers, Adder/Subtracter, Shifter, ALU, Register File

Single-Cycle CPU Design:
Multiple-Cycle CPU Design:
Pipelined CPU Design with Delayed Branch, Stall, and Forwarding:

MIPS Instructions
Bit #	31..26	25..21	20..16	15..11	10..6	5..0
R-type	op	rs	rt	rd	sa	func
add	000000	rs	rt	rd	00000	100000	rd <- rs + rt
sub	000000	rs	rt	rd	00000	100010	rd <- rs - rt
and	000000	rs	rt	rd	00000	100100	rd <- rs & rt
or	000000	rs	rt	rd	00000	100101	rd <- rs \| rt
sll	000000	00000	rt	rd	sa	000000	rd <- rt << sa
srl	000000	00000	rt	rd	sa	000010	rd <- rt >> sa (logical)
sra	000000	00000	rt	rd	sa	000011	rd <- rt >> sa (arithmetic)
I-type	op	rs	rt	immediate
addi	001000	rs	rt	immediate	rt <- rs + (sign-extend)immediate
andi	001100	rs	rt	immediate	rt <- rs & (zero-extend)immediate
ori	001101	rs	rt	immediate	rt <- rs \| (zero-extend)immediate
lw	100011	rs	rt	immediate	rt <- memory[rs + (sign-extend)immediate]
sw	101011	rs	rt	immediate	memory[rs + (sign-extend)immediate] <- rt
beq	000100	rs	rt	immediate	if (rs == rt) PC <- PC+4 + (sign-extend)immediate<<2
bne	000101	rs	rt	immediate	if (rs != rt) PC <- PC+4 + (sign-extend)immediate<<2
J-type	op	address
j	000010	address	PC <- (PC+4)[31..28],address,0,0

References

Workshops on Computer Architecture Education (WCAE-2)
``Using Computer Architecture/Organization at the University of Aizu'', Second Workshop on Computer Architecture Education, Feb. 3, 1996, San ose, California, U.S.A. Also see ``Using FPGA for Computer Architecture/Organization Education'', IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter, June 1996, IEEE Computer Society Press, pp.31-35. TCCA96JUNE.pdf
``Aizup -- A Pipelined Processor Design and Implementation on XILINX FPGA Chip'', Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, Apr.17-19, 1996, Napa, California, U.S.A. IEEE Computer Society Press, pp.98-106. FCCM96.pdf