`timescale 1ns/1ns
module modinv_r8_tb;
    reg          clk, rst_n, start;
    reg  [255:0] b, a, m;
    wire [255:0] c;
    wire         ready, busy, ready0;
    modinv_r8 inst (clk, rst_n, start, b, a, m, c, ready, busy, ready0);
    initial begin
        clk   = 1;
        rst_n = 0;
        start = 0;
        b = 256'h9cfa1c993911914be0f15bd74a878abe0079c6254b961b82e1abda76387d1d85;
        a = 256'hd5076ae274e874c2eb0f7778717c39460236549ddd9fc651e68a0c0e787b4ce8;
        m = 256'hfffffffffffffffffffffffffffffffffffffffffffffffffffffffefffffc2f;
        #1 rst_n = 1;
        #0 start = 1;
        #2 start = 0;
        wait(ready); // 416ns
        #40 $finish; // $stop;
    end
    always #1 clk = !clk;
    initial begin
        $dumpfile ("modinv_r8.vcd");
        $dumpvars;
    end
endmodule

/*
b = 0x9cfa1c993911914be0f15bd74a878abe0079c6254b961b82e1abda76387d1d85
a = 0xd5076ae274e874c2eb0f7778717c39460236549ddd9fc651e68a0c0e787b4ce8
m = 0xfffffffffffffffffffffffffffffffffffffffffffffffffffffffefffffc2f
c = 0xe8e5ac2e1d3358894ce1b3342737b38c39b89059dd55d3c4741626de8270228e
*/