`timescale 1ns/1ns
module vgac_tb;
    reg [11:0] d_in;
    reg        vga_clk;
    reg        clrn;
    wire [8:0] row_addr;
    wire [9:0] col_addr;
    wire [3:0] r,g,b;
    wire       rdn;
    wire       hs,vs;
    vgac monitor (vga_clk,clrn,d_in,row_addr,col_addr,rdn,r,g,b,hs,vs);
    initial begin
            vga_clk = 1;
            clrn    = 0;
            d_in    = 12'h5af;
        #10 clrn    = 1;
       #10000000 $stop;
    end
    always #10 vga_clk = !vga_clk;
endmodule
/*
       0 -     220 ns hs start
    1840 -    2060 ns hs end
  562780 -  563000 ns first pixel
 8399900 - 8400120 ns one frame
*/