// Single port synchronous RAM, by Li Yamin, yamin@ieee.org

module char_ram (clk,addr,dout,din,we); // single-port ram
    input         clk,we;
    input  [12:0] addr;
    input   [6:0] din;
    output  [6:0] dout;

    reg    [12:0] addr_reg;
    reg     [6:0] char_ram [0:4799];    // 80 * 60 = 4800
    always @(posedge clk) begin         // posedge read and write 
        if (we) begin
            char_ram[addr] <= din;      // write char ram
        end
        addr_reg <= addr;               // register read address
    end
    assign dout = char_ram[addr_reg];   // read char ram

    initial begin
        char_ram[13'd2354] = 7'h48;     // H
        char_ram[13'd2355] = 7'h65;     // e
        char_ram[13'd2356] = 7'h6c;     // l
        char_ram[13'd2357] = 7'h6c;     // l
        char_ram[13'd2358] = 7'h6f;     // o
        char_ram[13'd2359] = 7'h2c;     // ,
        char_ram[13'd2360] = 7'h20;     // 
        char_ram[13'd2361] = 7'h46;     // F
        char_ram[13'd2362] = 7'h50;     // P
        char_ram[13'd2363] = 7'h47;     // G
        char_ram[13'd2364] = 7'h41;     // A
        char_ram[13'd2365] = 7'h21;     // !
    end
endmodule