TABLE OF CONTENTS (HIDE)

Verilog HDL, Switch, Button, and LED

A simple circuit

Design the following circuit in Verilog HDL and implement it on DE0-CV FPGA board. 

switch-led.svg

Implementation on DE0-CV with Quartus II

Step 1: Start Altera - Quartus II 13.1. If Quartus II 13.1 was not installed on your PC, download it from either CIS Storage Server or Intel FPGA Software Download Center and install it.

Step 2: In Quartus II, File - New Project Wizard.

Step 3: Set working directory to D:\projects.

Step 4: Set the name of the project to sw_led. 

  new_project_1.png

Step 5: If sw_led.v exists, add file sw_led.v (only sw_led.v. The sw_led_tb.v is just for simulation with ModelSim). 

  new_project_2.png

Step 6: Set device to Cyclone V - 5CEBA4F23C7 (FPGA chip in DE0-CV board). 

  new_project_3.png

Step 7: Click Finish.

Step 8: If sw_led.v does not exist, create file sw_led.v.
File - New - Verilog HDL File - OK
Add the following to the editor window and save it to sw_led.v.
Project - Add current File to Project 

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module sw_led (
    input  [1:0] sw, // 2 switches
    output [9:0] led // 10 LEDs
  );

  assign led[0] =   sw[1]  & sw[0];  //      b  AND a
  assign led[1] = ~(sw[1]  & sw[0]); // NOT (b  AND a)
  assign led[2] =   sw[1]  | sw[0];  //      b   OR a
  assign led[3] = ~(sw[1]  | sw[0]); // NOT (b   OR a)
  assign led[4] =   sw[1]  ^ sw[0];  //      b  XOR a
  assign led[5] = ~(sw[1]  ^ sw[0]); // NOT (b  XOR a)
  assign led[6] =          ~ sw[0];  // NOT         a
  assign led[7] = ~ sw[1];           // NOT  b
  assign led[8] =   sw[1] ~^ sw[0];  //      b NXOR a
  assign led[9] = ~(sw[1] ~^ sw[0]); // NOT (b NXOR a)
endmodule

Step 9: In Quartus II, Ctrl+k (analysis and synthesis).

Step 10: In Quartus II, Assignments - Pin Planner.

Step 11: Referring to User Manual, assign pins as below (set pin names in Location column).

Ex. pin_name of LED[0] is PIN_AA2 (See Table 3-4 of p.22 in User Manual). 

sw_led.pin.png

Or add the following to sw_led.qsf. 

set_location_assignment PIN_U13 -to sw[0]
set_location_assignment PIN_V13 -to sw[1]
set_location_assignment PIN_AA2 -to led[0]
set_location_assignment PIN_AA1 -to led[1]
set_location_assignment PIN_W2 -to led[2]
set_location_assignment PIN_Y3 -to led[3]
set_location_assignment PIN_N2 -to led[4]
set_location_assignment PIN_N1 -to led[5]
set_location_assignment PIN_U2 -to led[6]
set_location_assignment PIN_U1 -to led[7]
set_location_assignment PIN_L2 -to led[8]
set_location_assignment PIN_L1 -to led[9]

Step 12: In Quartus II, Ctrl+l (full compile).

Step 13: Connect DE0-CV board to your PC with Type A to B USB Cable.

Step 14: Push Red Button to power on DE0-CV board. No need to use AC adaptor; the power is suplied by USB.

Install USB-Blaster Driver (only one time, steps 14 - 18):

Step 15: Start Device Manager (right-click Win10 Start Button or Win+x). 

start-computer-device.png

Step 16: Update Altera USB-Blaster Driver (right-click). Note that it may appear in a different place. 

device-manager.png

Step 17: Find the driver in this PC. 

search-driver.png

Step 18: Input driver path C:\altera\13.1\quartus\drivers and then click Next. Note that the driver may be in a different place in your PC, for example, in C:\Software\quartus\quartus\drivers. 

driver-path.png

Step 19: Installed. 

blster-installed.png

Step 20: In Quartus II, Tools - Programmer.

Step 21: Hardware Setup: select USB-Blaster.

Step 22: Click Start button to program FPGA Chip. In case there is no file name displied, click Add File button to load output_files/sw_led.sof.

Step 23: On DE0-CV board, switch sw[0] and sw[1] to see the changes of LEDs. 

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module sw_led (
    input  [1:0] sw, // 2 switches
    output [9:0] led // 10 LEDs
  );

  assign led[0] =   sw[1]  & sw[0];  //      b  AND a
  assign led[1] = ~(sw[1]  & sw[0]); // NOT (b  AND a)
  assign led[2] =   sw[1]  | sw[0];  //      b   OR a
  assign led[3] = ~(sw[1]  | sw[0]); // NOT (b   OR a)
  assign led[4] =   sw[1]  ^ sw[0];  //      b  XOR a
  assign led[5] = ~(sw[1]  ^ sw[0]); // NOT (b  XOR a)
  assign led[6] =          ~ sw[0];  // NOT         a
  assign led[7] = ~ sw[1];           // NOT  b
  assign led[8] =   sw[1] ~^ sw[0];  //      b NXOR a
  assign led[9] = ~(sw[1] ~^ sw[0]); // NOT (b NXOR a)
endmodule

Step 20: Hardware Setup: If there is no USB-Blaster

Windows 11: Start --> 設定 --> プライバシーとセキュリティ --> Windows セキュリティ --> デバイス セキュリティ --> コア分離の詳細 --> メモリ整合性: オフ --> PCを再起動 

memory-integrity.png

Exercise

Design the following circuit in Verilog HDL and implement it on DE0-CV FPGA board. 

switch_button_mux2x1.svg
  1. First, create a new project with the project name "switch_button_mux2x1". Note that we do not create a new folder for it. All projects share the same "projects" folder.
  2. Referring to the figure above, complete and compile the following Verilog HDL code with ModelSim. The file name is switch_button_mux2x1.v. 

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    module switch_button_mux2x1 (
    input  A, B, SEL, // SEL: Select
    output Y
  );

  // assign Y = ...;

endmodule
  3. Implement switch_button_mux2x1.v on the FPGA board (using two buttons and a switch as inputs and a LED as output).
    Pin assignments: 
    set_location_assignment PIN_U13 -to SEL
set_location_assignment PIN_U7 -to A
set_location_assignment PIN_W9 -to B
set_location_assignment PIN_AA2 -to Y

Reference

DE0-CV FPGA Board User Manual.

Latest version tested: Altera Quartus II 13.1 (64-bit) and ModelSim-Altera 10.1d
Last modified: April, 2023