%\documentclass[dvipdfmx,t,serif,mathserif,14pt]{beamer} % t: from top; serif: rmdefault
\documentclass[dvipdfmx,t,14pt]{beamer} % t: from top; serif: rmdefault
\usepackage{mybeamer}

\newcommand{\PDFTITLE}{論理回路入門（10）}
\newcommand{\PDFSUBJECT}{一年生秋学期}
\newcommand{\PDFAUTHOR}{法政大学情報科学部}
\newcommand{\PDFKEYWORDS}{
  デコーダ、
  イネーブル付きデコーダ、
  デマルチプレクサ、
  エンコーダ、
  イネーブル付きエンコーダ、
  プライオリティエンコーダ}

\date{2023 年 11 月 28 日 (火)}

\title{\PDFTITLE} % bottom PDFTITLE
\subtitle{デコーダとエンコーダ}
\author[\PDFAUTHOR]{李　亜民}% bottom PDFAUTHOR; titlepage Yamin Li

\hypersetup{
  pdftitle=\PDFTITLE,
  pdfsubject=\PDFSUBJECT,
  pdfauthor=\PDFAUTHOR,
  pdfkeywords=\PDFKEYWORDS
}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{document}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\everymath={\sf}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{\PDFTITLE}
\begin{frame}
  \titlepage
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%------------------------------------------------ SLIDE -
\input{mybackgroundcolor.tex}
%------------------------------------------------ SLIDE -
\section{デコーダとエンコーダ}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}

  \textcolor{blue}{ポイント}

\vspace{3mm}
\begin{itemize}
\setlength{\itemsep}{2.6mm}
  \blue 
\item デコーダ (\textcolor{red}{$n \Rightarrow 2^n$})
\item イネーブル付きデコーダ
\item デマルチプレクサ

\vspace{13mm}
\item エンコーダ (\textcolor{red}{$2^n \Rightarrow n$})
\item イネーブル付きエンコーダ
\item プライオリティエンコーダ
\end{itemize}

\vspace{-70mm}
\hspace*{80mm}
\includegraphics[scale=.5]{figs/decoder.pdf}

\vspace{2mm}
\hspace*{80mm}
\includegraphics[scale=.5]{figs/encoder.pdf}

\end{frame}
%------------------------------------------------ SLIDE -
\section{3 入力~8 出力デコーダ}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
  \color{DarkOrchid}
  \vspace{5mm}
  \begin{center}
    \scalebox{2.6}[2.6]{３入力８出力}

\vspace{8mm}
    \scalebox{2.7}[2.7]{デコーダ}

\vspace{8mm}
    \scalebox{2.7}[2.7]{の設計}
  \end{center}
\end{frame}
%------------------------------------------------ SLIDE -
\section{3 入力~8 出力デコーダ~(真理値表)}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{14}\selectfont
3 入力~8 出力デコーダ: ~ 3 入力~(d[2:0]) を~2 進数について、その~10 進数に対応する~8 個の出力~(n[7:0]) を生成する回路。

\vspace{5mm}
真理値表:

\vspace{2mm}
\setlength{\tabcolsep}{2.1pt}
\begin{tabular}{cccccccccccc}\hline
\multicolumn{3}{c}{\rule{0pt}{.8\normalbaselineskip}入力}&&\multicolumn{8}{c}{出力}\\\cline{1-3}\cline{5-12}
\rule{0pt}{.8\normalbaselineskip}d[2]&d[1]&d[0]&&n[7]&n[6]&n[5]&n[4]&n[3]&n[2]&n[1]&n[0]\\\cline{1-3}\cline{5-12}
\rule{0pt}{.8\normalbaselineskip}%
0 & 0 & 0 && 0 & 0 & 0 & 0 & 0 & 0 & 0 &\red 1\\
0 & 0 & 1 && 0 & 0 & 0 & 0 & 0 & 0 &\red 1 & 0\\
0 & 1 & 0 && 0 & 0 & 0 & 0 & 0 &\red 1 & 0 & 0\\
0 & 1 & 1 && 0 & 0 & 0 & 0 &\red 1 & 0 & 0 & 0\\
1 & 0 & 0 && 0 & 0 & 0 &\red 1 & 0 & 0 & 0 & 0\\
1 & 0 & 1 && 0 & 0 &\red 1 & 0 & 0 & 0 & 0 & 0\\
1 & 1 & 0 && 0 &\red 1 & 0 & 0 & 0 & 0 & 0 & 0\\
1 & 1 & 1 &&\red 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0\\\hline
\end{tabular}
\end{frame}
%------------------------------------------------ SLIDE -
\section{3 入力~8 出力デコーダ~(論理式)}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{14}\selectfont
\setlength{\tabcolsep}{2.1pt}
\begin{tabular}{cccccccccccc}\hline
\multicolumn{3}{c}{\rule{0pt}{.8\normalbaselineskip}入力}&&\multicolumn{8}{c}{出力}\\\cline{1-3}\cline{5-12}
\rule{0pt}{.8\normalbaselineskip}d[2]&d[1]&d[0]&&n[7]&n[6]&n[5]&n[4]&n[3]&n[2]&n[1]&n[0]\\\cline{1-3}\cline{5-12}
\rule{0pt}{.8\normalbaselineskip}%
0 & 0 & 0 && 0 & 0 & 0 & 0 & 0 & 0 & 0 &\red 1\\[-3pt]
0 & 0 & 1 && 0 & 0 & 0 & 0 & 0 & 0 &\red 1 & 0\\[-3pt]
0 & 1 & 0 && 0 & 0 & 0 & 0 & 0 &\red 1 & 0 & 0\\[-3pt]
0 & 1 & 1 && 0 & 0 & 0 & 0 &\red 1 & 0 & 0 & 0\\[-3pt]
1 & 0 & 0 && 0 & 0 & 0 &\red 1 & 0 & 0 & 0 & 0\\[-3pt]
1 & 0 & 1 && 0 & 0 &\red 1 & 0 & 0 & 0 & 0 & 0\\[-3pt]
1 & 1 & 0 && 0 &\red 1 & 0 & 0 & 0 & 0 & 0 & 0\\[-3pt]
1 & 1 & 1 &&\red 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0\\\hline
\end{tabular}

\vspace{3mm}
$n\mbox{[}0\mbox{]}=\overline{d\mbox{[}2\mbox{]}} \ \overline{d\mbox{[}1\mbox{]}} \ \overline{d\mbox{[}0\mbox{]}}$
\hspace{27mm}
$n\mbox{[}4\mbox{]}={d\mbox{[}2\mbox{]}} \ \overline{d\mbox{[}1\mbox{]}} \ \overline{d\mbox{[}0\mbox{]}}$

\vspace{2mm}
$n\mbox{[}1\mbox{]}=\overline{d\mbox{[}2\mbox{]}} \ \overline{d\mbox{[}1\mbox{]}} \ {d\mbox{[}0\mbox{]}}$
\hspace{27mm}
$n\mbox{[}5\mbox{]}={d\mbox{[}2\mbox{]}} \ \overline{d\mbox{[}1\mbox{]}} \ {d\mbox{[}0\mbox{]}}$

\vspace{2mm}
$n\mbox{[}2\mbox{]}=\overline{d\mbox{[}2\mbox{]}} \ {d\mbox{[}1\mbox{]}} \ \overline{d\mbox{[}0\mbox{]}}$
\hspace{27mm}
$n\mbox{[}6\mbox{]}={d\mbox{[}2\mbox{]}} \ {d\mbox{[}1\mbox{]}} \ \overline{d\mbox{[}0\mbox{]}}$

\vspace{2mm}
$n\mbox{[}3\mbox{]}=\overline{d\mbox{[}2\mbox{]}} \ {d\mbox{[}1\mbox{]}} \ {d\mbox{[}0\mbox{]}}$
\hspace{27mm}
$n\mbox{[}7\mbox{]}={d\mbox{[}2\mbox{]}} \ {d\mbox{[}1\mbox{]}} \ {d\mbox{[}0\mbox{]}}$

\end{frame}
%------------------------------------------------ SLIDE -
\section{3 入力~8 出力デコーダ~(回路)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{13}\selectfont
\begin{code}
`timescale 1ns/1ns
module dec38 (d, n);
    input  [2:0] d;
    output [7:0] n;

    assign n[0] = ~d[2] & ~d[1] & ~d[0]; // 000
    assign n[1] = ~d[2] & ~d[1] &  d[0]; // 001
    assign n[2] = ~d[2] &  d[1] & ~d[0]; // 010
    assign n[3] = ~d[2] &  d[1] &  d[0]; // 011
    assign n[4] =  d[2] & ~d[1] & ~d[0]; // 100
    assign n[5] =  d[2] & ~d[1] &  d[0]; // 101
    assign n[6] =  d[2] &  d[1] & ~d[0]; // 110
    assign n[7] =  d[2] &  d[1] &  d[0]; // 111

endmodule
\end{code}

\vspace{-9mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/dec38.v}{\color{blue}\underline{dec38.v}}~~~

\end{frame}
%------------------------------------------------ slide -
\section{3 入力~8 出力デコーダ~(テストベンチ)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{13}\selectfont
\begin{code}
`timescale 1ns/1ns
module dec38_tb;
    reg  [2:0] d;
    wire [7:0] n;
    dec38 i0 (d, n);
    initial begin
        #0 d = 0;
        #8 $finish;
    end
    always #1 d = d + 1;
    initial begin
        $dumpfile ("dec38.vcd");
        $dumpvars;
    end
endmodule
\end{code}

\vspace{-9mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/dec38_tb.v}{\color{blue}\underline{dec38\_tb.v}}~~~

\end{frame}
%------------------------------------------------ slide -
\section{3 入力~8 出力デコーダ~(波形)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\vspace{-5mm}
\begin{verbatim}
% iverilog -Wall -o dec38 dec38_tb.v dec38.v
% ./dec38
% gtkwave dec38.vcd
\end{verbatim}

\vspace{2mm}
\includegraphics[width=\textwidth]{figs/dec38_vcd_crop.png}

\fontsize{8pt}{10}\selectfont
入力：
\hspace{5mm}$d=\textcolor{red}{0}$
\hspace{5mm}$d=\textcolor{red}{1}$
\hspace{5mm}$d=\textcolor{red}{2}$
\hspace{5mm}$d=\textcolor{red}{3}$
\hspace{5mm}$d=\textcolor{red}{4}$
\hspace{5mm}$d=\textcolor{red}{5}$
\hspace{5mm}$d=\textcolor{red}{6}$
\hspace{5mm}$d=\textcolor{red}{7}$

出力：
\hspace{4mm}$n\mbox{[}\textcolor{red}{0}\mbox{]}$$=$$\textcolor{blue}{1}$
\hspace{3mm}$n\mbox{[}\textcolor{red}{1}\mbox{]}$$=$$\textcolor{blue}{1}$
\hspace{3mm}$n\mbox{[}\textcolor{red}{2}\mbox{]}$$=$$\textcolor{blue}{1}$
\hspace{3mm}$n\mbox{[}\textcolor{red}{3}\mbox{]}$$=$$\textcolor{blue}{1}$
\hspace{3mm}$n\mbox{[}\textcolor{red}{4}\mbox{]}$$=$$\textcolor{blue}{1}$
\hspace{3mm}$n\mbox{[}\textcolor{red}{5}\mbox{]}$$=$$\textcolor{blue}{1}$
\hspace{3mm}$n\mbox{[}\textcolor{red}{6}\mbox{]}$$=$$\textcolor{blue}{1}$
\hspace{3mm}$n\mbox{[}\textcolor{red}{7}\mbox{]}$$=$$\textcolor{blue}{1}$

\end{frame}
%------------------------------------------------ SLIDE -
\section{イネーブル付き3-8デコーダ}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\fontsize{11pt}{14}\selectfont
\setlength{\tabcolsep}{2.1pt}
\begin{tabular}{ccccccccccccc}\hline
\multicolumn{4}{c}{\rule{0pt}{.8\normalbaselineskip}入力}&&\multicolumn{8}{c}{出力}\\\cline{1-4}\cline{6-13}
\rule{0pt}{.8\normalbaselineskip}%
\blue e&d[2]&d[1]&d[0]&&n[7]&n[6]&n[5]&n[4]&n[3]&n[2]&n[1]&n[0]\\\cline{1-4}\cline{6-13}
\rule{0pt}{.8\normalbaselineskip}%
\blue 1 & 0 & 0 & 0 && 0 & 0 & 0 & 0 & 0 & 0 & 0 &\red 1\\[-3pt]
\blue 1 & 0 & 0 & 1 && 0 & 0 & 0 & 0 & 0 & 0 &\red 1 & 0\\[-3pt]
\blue 1 & 0 & 1 & 0 && 0 & 0 & 0 & 0 & 0 &\red 1 & 0 & 0\\[-3pt]
\blue 1 & 0 & 1 & 1 && 0 & 0 & 0 & 0 &\red 1 & 0 & 0 & 0\\[-3pt]
\blue 1 & 1 & 0 & 0 && 0 & 0 & 0 &\red 1 & 0 & 0 & 0 & 0\\[-3pt]
\blue 1 & 1 & 0 & 1 && 0 & 0 &\red 1 & 0 & 0 & 0 & 0 & 0\\[-3pt]
\blue 1 & 1 & 1 & 0 && 0 &\red 1 & 0 & 0 & 0 & 0 & 0 & 0\\[-3pt]
\blue 1 & 1 & 1 & 1 &&\red 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0\\[-3pt]
\red 0 &\red x &\red x &\red x && 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0\\\hline
\end{tabular}

\vspace{2mm}
\textcolor{blue}{e: enable}; ~ \textcolor{red}{x}: ドントケア~(Don't care)

\vspace{2mm}
$n\mbox{[}0\mbox{]}=\textcolor{blue}e \ \overline{d\mbox{[}2\mbox{]}} \ \overline{d\mbox{[}1\mbox{]}} \ \overline{d\mbox{[}0\mbox{]}}$
\hspace{23mm}
$n\mbox{[}4\mbox{]}=\textcolor{blue}e \ {d\mbox{[}2\mbox{]}} \ \overline{d\mbox{[}1\mbox{]}} \ \overline{d\mbox{[}0\mbox{]}}$

\vspace{.1mm}
$n\mbox{[}1\mbox{]}=\textcolor{blue}e \ \overline{d\mbox{[}2\mbox{]}} \ \overline{d\mbox{[}1\mbox{]}} \ {d\mbox{[}0\mbox{]}}$
\hspace{23mm}
$n\mbox{[}5\mbox{]}=\textcolor{blue}e \ {d\mbox{[}2\mbox{]}} \ \overline{d\mbox{[}1\mbox{]}} \ {d\mbox{[}0\mbox{]}}$

\vspace{.1mm}
$n\mbox{[}2\mbox{]}=\textcolor{blue}e \ \overline{d\mbox{[}2\mbox{]}} \ {d\mbox{[}1\mbox{]}} \ \overline{d\mbox{[}0\mbox{]}}$
\hspace{23mm}
$n\mbox{[}6\mbox{]}=\textcolor{blue}e \ {d\mbox{[}2\mbox{]}} \ {d\mbox{[}1\mbox{]}} \ \overline{d\mbox{[}0\mbox{]}}$

\vspace{.1mm}
$n\mbox{[}3\mbox{]}=\textcolor{blue}e \ \overline{d\mbox{[}2\mbox{]}} \ {d\mbox{[}1\mbox{]}} \ {d\mbox{[}0\mbox{]}}$
\hspace{23mm}
$n\mbox{[}7\mbox{]}=\textcolor{blue}e \ {d\mbox{[}2\mbox{]}} \ {d\mbox{[}1\mbox{]}} \ {d\mbox{[}0\mbox{]}}$

\end{frame}
%------------------------------------------------ SLIDE -
\section{イネーブル付き3-8デコーダ~(回路)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\fontsize{11pt}{12}\selectfont
\begin{code}
`timescale 1ns/1ns
module dec38e (d, e, n);
    input  [2:0] d;
    input        e;
    output [7:0] n;

    assign n[0] = e & ~d[2] & ~d[1] & ~d[0]; // 1_000
    assign n[1] = e & ~d[2] & ~d[1] &  d[0]; // 1_001
    assign n[2] = e & ~d[2] &  d[1] & ~d[0]; // 1_010
    assign n[3] = e & ~d[2] &  d[1] &  d[0]; // 1_011
    assign n[4] = e &  d[2] & ~d[1] & ~d[0]; // 1_100
    assign n[5] = e &  d[2] & ~d[1] &  d[0]; // 1_101
    assign n[6] = e &  d[2] &  d[1] & ~d[0]; // 1_110
    assign n[7] = e &  d[2] &  d[1] &  d[0]; // 1_111

endmodule
\end{code}

\vspace{-9mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/dec38e.v}{\color{blue}\underline{dec38e.v}}~~~

\end{frame}
%------------------------------------------------ slide -
\section{イネーブル付き3-8デコーダ~(テストベンチ)}
\begin{frame}[fragile]\frametitle{\scalebox{.88}{\secname}}
\fontsize{8pt}{8.35}\selectfont
\begin{code}
`timescale 1ns/1ns
module dec38e_tb;
    reg  [2:0] d;
    reg        e;
    wire [7:0] n;
    dec38e i0 (d, e, n);
    initial begin
        #0 d = 3'b000; e = 1'b1;
        #1 d = 3'b001;
        #1 d = 3'b010;
        #1 d = 3'b011;
        #1 d = 3'b100;
        #1 d = 3'b101;
        #1 d = 3'b110;
        #1 d = 3'b111;
        #1 d = 3'bxxx; e = 1'b0;
        #1 $finish;
    end
    initial begin
        $dumpfile ("dec38e.vcd");
        $dumpvars;
    end
endmodule
\end{code}

\vspace{-9mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/dec38e_tb.v}{\color{blue}\underline{dec38e\_tb.v}}~~~

\end{frame}
%------------------------------------------------ slide -
\section{イネーブル付き3-8デコーダ~(波形)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\vspace{-5mm}
\begin{verbatim}
% iverilog -Wall -o dec38e dec38e_tb.v dec38e.v
% ./dec38e
% gtkwave dec38e.vcd
\end{verbatim}

\vspace{2mm}
\includegraphics[width=\textwidth]{figs/dec38e_vcd_crop.png}

\fontsize{8pt}{10}\selectfont
\hfill $e=0$~~~~

\hfill $n=00000000$

\end{frame}
%------------------------------------------------ SLIDE -
\section{デコーダの応用 --- RegFile}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\includegraphics[width=\textwidth]{figs/computer_alu.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{デコーダの応用 --- RegFile}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\textcolor{red}{8 $\times$ 32 ビットレジスタ・ファイル}

\includegraphics[width=\textwidth]{figs/regfile8x32_schematic.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{デコーダの応用 --- デマルチプレクサ}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\textcolor{red}{マルチプレクサ\hspace{34mm}デマルチプレクサ}

\vspace{3mm}
\includegraphics[width=\textwidth]{figs/demux.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{デコーダの応用 --- デマルチプレクサ}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\textcolor{red}{マルチプレクサ\hspace{20mm}デマルチプレクサ}

\vspace{3mm}
\fontsize{11pt}{17}\selectfont
\tabcolsep=3pt
\begin{tabular}{c|ccc|cccccccc}
\multicolumn{2}{c}{真理値表}&&\multicolumn{9}{c}{真理値表}\\\cline{1-2}\cline{4-12}
\rule{0pt}{.8\normalbaselineskip}s[2:0]&Y&~~~~~~~&s[2:0]&w7&w6&w5&w4&w3&w2&w1&w0\\\cline{1-2}\cline{4-12}
\rule{0pt}{.8\normalbaselineskip}%
0~~0~~0&a0&&0~~0~~0&0&0&0&0&0&0&0&\red we\\
0~~0~~1&a1&&0~~0~~1&0&0&0&0&0&0&\red we&0\\
0~~1~~0&a2&&0~~1~~0&0&0&0&0&0&\red we&0&0\\
0~~1~~1&a3&&0~~1~~1&0&0&0&0&\red we&0&0&0\\\cline{1-2}\cline{4-12}
\rule{0pt}{.8\normalbaselineskip}%
1~~0~~0&a4&&1~~0~~0&0&0&0&\red we&0&0&0&0\\
1~~0~~1&a5&&1~~0~~1&0&0&\red we&0&0&0&0&0\\
1~~1~~0&a6&&1~~1~~0&0&\red we&0&0&0&0&0&0\\
1~~1~~1&a7&&1~~1~~1&\red we&0&0&0&0&0&0&0\\\cline{1-2}\cline{4-12}
\end{tabular}
\end{frame}
%------------------------------------------------ SLIDE -
\section{デコーダの応用 --- デマルチプレクサ}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\textcolor{red}{デマルチプレクサの回路}

\vspace{3mm}
\includegraphics[width=\textwidth]{figs/demux_decoder.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{デマルチプレクサ (回路)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\fontsize{11pt}{11.5}\selectfont
\begin{code}
`timescale 1ns/1ns
module demux8x1 (we, s, w);
    input  [2:0] s;
    input        we;
    output [7:0] w;

    wire   [7:0] n;
    dec38 i0 (s, n);

    assign w = n & {8{we}};

endmodule





\end{code}

\vspace{-9mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/demux8x1.v}{\color{blue}\underline{demux8x1.v}}~~~

\end{frame}
%------------------------------------------------ slide -
\section{デマルチプレクサ (テストベンチ)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\fontsize{11pt}{11.5}\selectfont
\begin{code}
`timescale 1ns/1ns
module demux8x1_tb;
    reg  [2:0] s;
    reg        we;
    wire [7:0] w;
    demux8x1 i0 (we, s, w);
    initial begin
        #0 s = 0; we = 1;
        #8 we = 0;
        #1 $finish;
    end
    always #1 s = s + 1;
    initial begin
        $dumpfile ("demux8x1.vcd");
        $dumpvars;
    end
endmodule
\end{code}

\vspace{-9mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/demux8x1_tb.v}{\color{blue}\underline{demux8x1\_tb.v}}~~~

\end{frame}
%------------------------------------------------ slide -
\section{デマルチプレクサ (波形)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\vspace{-5mm}
\begin{verbatim}
% iverilog -Wall -o demux8x1 \
  demux8x1_tb.v dec38.v
% ./demux8x1
% gtkwave demux8x1.vcd
\end{verbatim}

\vspace{2mm}
\includegraphics[width=\textwidth]{figs/demux8x1_vcd_crop.png}


\fontsize{8pt}{10}\selectfont
入力：
\hspace{5mm}$s=\textcolor{red}{0}$
\hspace{4mm}$s=\textcolor{red}{1}$
\hspace{4mm}$s=\textcolor{red}{2}$
\hspace{4mm}$s=\textcolor{red}{3}$
\hspace{4mm}$s=\textcolor{red}{4}$
\hspace{4mm}$s=\textcolor{red}{5}$
\hspace{4mm}$s=\textcolor{red}{6}$
\hspace{4mm}$s=\textcolor{red}{7}$
\hspace{4mm}$s=\textcolor{red}{0}$

出力：\fontsize{6pt}{10}\selectfont
\hspace{4.0mm}$w\mbox{[}\textcolor{red}{0}\mbox{]}$$=$$\textcolor{blue}{we}$
\hspace{2.2mm}$w\mbox{[}\textcolor{red}{1}\mbox{]}$$=$$\textcolor{blue}{we}$
\hspace{2.2mm}$w\mbox{[}\textcolor{red}{2}\mbox{]}$$=$$\textcolor{blue}{we}$
\hspace{2.2mm}$w\mbox{[}\textcolor{red}{3}\mbox{]}$$=$$\textcolor{blue}{we}$
\hspace{2.2mm}$w\mbox{[}\textcolor{red}{4}\mbox{]}$$=$$\textcolor{blue}{we}$
\hspace{2.2mm}$w\mbox{[}\textcolor{red}{5}\mbox{]}$$=$$\textcolor{blue}{we}$
\hspace{2.2mm}$w\mbox{[}\textcolor{red}{6}\mbox{]}$$=$$\textcolor{blue}{we}$
\hspace{2.2mm}$w\mbox{[}\textcolor{red}{7}\mbox{]}$$=$$\textcolor{blue}{we}$
\hspace{2.2mm}$w\mbox{[}\textcolor{red}{0}\mbox{]}$$=$$\textcolor{blue}{we}$

\end{frame}
%------------------------------------------------ SLIDE -
\section{デコーダの応用 --- SRAM デコーダ}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}

\includegraphics[width=\textwidth]{figs/decoder_ram.pdf}

\blue
\vspace{-12mm}
4 words $\times$

5 bits SRAM
\end{frame}
%------------------------------------------------ SLIDE -
\section{デマルチプレクサの応用 --- SRAM 書き込む}
\begin{frame}\frametitle{\resizebox{\textwidth}{!}{\secname}}
\includegraphics[width=\textwidth]{figs/d_latch_memory.pdf}

\fontsize{9pt}{11}\selectfont

\blue
\vspace{-3mm}
we: write enable

4 words: 2-bit address A[1:0]: $2^2=4$

5 bits\,/\,word: data-in DI[4:0]; data-out DO[4:0]
\end{frame}
%------------------------------------------------ SLIDE -
\section{8 入力~3 出力エンコーダ}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
  \color{DarkOrchid}
  \vspace{5mm}
  \begin{center}
    \scalebox{2.6}[2.6]{８入力３出力}

\vspace{8mm}
    \scalebox{2.7}[2.7]{エンコーダ}

\vspace{8mm}
    \scalebox{2.7}[2.7]{の設計}
  \end{center}
\end{frame}
%------------------------------------------------ SLIDE -
\section{8 入力~3 出力エンコーダ~(真理値表)}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\fontsize{13pt}{15}\selectfont
8 入力~3 出力エンコーダ: ~ 8 入力~(d[7:0]) のいずれか一つが値~1 をとるものとして、それらの~2 進数に対応する~3 ビットの出力~(n[2:0]) を生成する回路。真理値表:

\vspace{2mm}
\fontsize{12pt}{14}\selectfont
\setlength{\tabcolsep}{2.2pt}
\begin{tabular}{cccccccccccc}\hline
\multicolumn{8}{c}{\rule{0pt}{.8\normalbaselineskip}入力\textcolor{red}{（制限あり）}}&&\multicolumn{3}{c}{出力}\\\cline{1-8}\cline{10-12}
\rule{0pt}{.8\normalbaselineskip}d[7]&d[6]&d[5]&d[4]&d[3]&d[2]&d[1]&d[0]&&n[2]&n[1]&n[0]\\\cline{1-8}\cline{10-12}
\rule{0pt}{.8\normalbaselineskip}%
 0 & 0 & 0 & 0 & 0 & 0 & 0 &\red 1 && 0 & 0 & 0\\
 0 & 0 & 0 & 0 & 0 & 0 &\red 1 & 0 && 0 & 0 & 1\\
 0 & 0 & 0 & 0 & 0 &\red 1 & 0 & 0 && 0 & 1 & 0\\
 0 & 0 & 0 & 0 &\red 1 & 0 & 0 & 0 && 0 & 1 & 1\\
 0 & 0 & 0 &\red 1 & 0 & 0 & 0 & 0 && 1 & 0 & 0\\
 0 & 0 &\red 1 & 0 & 0 & 0 & 0 & 0 && 1 & 0 & 1\\
 0 &\red 1 & 0 & 0 & 0 & 0 & 0 & 0 && 1 & 1 & 0\\
\red 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 && 1 & 1 & 1\\\hline
\end{tabular}

\vspace{2mm}
\textcolor{red}{入力制限: 一つの入力のみがアクティブである}
\end{frame}
%------------------------------------------------ SLIDE -
\section{8 入力~3 出力エンコーダ~(論理式)}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\vspace{2mm}
\fontsize{12pt}{14}\selectfont
\setlength{\tabcolsep}{2.2pt}
\begin{tabular}{cccccccccccc}\hline
\multicolumn{8}{c}{\rule{0pt}{.8\normalbaselineskip}入力\textcolor{red}{（制限あり）}}&&\multicolumn{3}{c}{出力}\\\cline{1-8}\cline{10-12}
\rule{0pt}{.8\normalbaselineskip}d[7]&d[6]&d[5]&d[4]&d[3]&d[2]&d[1]&d[0]&&n[2]&n[1]&n[0]\\\cline{1-8}\cline{10-12}
\rule{0pt}{.8\normalbaselineskip}%
 0 & 0 & 0 & 0 & 0 & 0 & 0 &\red 1 && 0 & 0 & 0\\
 0 & 0 & 0 & 0 & 0 & 0 &\red 1 & 0 && 0 & 0 & 1\\
 0 & 0 & 0 & 0 & 0 &\red 1 & 0 & 0 && 0 & 1 & 0\\
 0 & 0 & 0 & 0 &\red 1 & 0 & 0 & 0 && 0 & 1 & 1\\
 0 & 0 & 0 &\red 1 & 0 & 0 & 0 & 0 && 1 & 0 & 0\\
 0 & 0 &\red 1 & 0 & 0 & 0 & 0 & 0 && 1 & 0 & 1\\
 0 &\red 1 & 0 & 0 & 0 & 0 & 0 & 0 && 1 & 1 & 0\\
\red 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 && 1 & 1 & 1\\\hline
\end{tabular}

\vspace{3mm}
$n\mbox{[}0\mbox{]}=d\mbox{[}1\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}7\mbox{]}$ \textcolor{red}{\hspace{13mm}入力制限: }

\vspace{2mm}
$n\mbox{[}1\mbox{]}=d\mbox{[}2\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}$ \textcolor{red}{\hspace{13mm}一つの入力のみが}

\vspace{2mm}
$n\mbox{[}2\mbox{]}=d\mbox{[}4\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}$ \textcolor{red}{\hspace{13mm}アクティブである}

\end{frame}
%------------------------------------------------ SLIDE -
\section{8 入力~3 出力エンコーダ~(回路)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{14}\selectfont
$n\mbox{[}0\mbox{]}=d\mbox{[}1\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}7\mbox{]}$

\vspace{1mm}
$n\mbox{[}1\mbox{]}=d\mbox{[}2\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}$

\vspace{1mm}
$n\mbox{[}2\mbox{]}=d\mbox{[}4\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}$

\vspace{3.6mm}
\begin{code}
`timescale 1ns/1ns
module enc83 (d, n);
    input  [7:0] d;
    output [2:0] n;

    assign n[0] = d[1] | d[3] | d[5] | d[7];
    assign n[1] = d[2] | d[3] | d[6] | d[7];
    assign n[2] = d[4] | d[5] | d[6] | d[7];

endmodule
\end{code}

\vspace{-9mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/enc83.v}{\color{blue}\underline{enc83.v}}~~~

\end{frame}
%------------------------------------------------ SLIDE -
\section{8 入力~3 出力エンコーダ~(テストベンチ)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\fontsize{9pt}{9}\selectfont
\begin{code}
`timescale 1ns/1ns
module enc83_tb;
    reg  [7:0] d;
    wire [2:0] n;
    enc83 i0 (d, n);
    initial begin
        #0 d = 8'b00000000;
        #1 d = 8'b00000001;
        #1 d = 8'b00000010;
        #1 d = 8'b00000100;
        #1 d = 8'b00001000;
        #1 d = 8'b00010000;
        #1 d = 8'b00100000;
        #1 d = 8'b01000000;
        #1 d = 8'b10000000;
        #1 $finish;
    end
    initial begin
        $dumpfile ("enc83.vcd");
        $dumpvars;
    end
endmodule
\end{code}

\vspace{-8mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/enc83_tb.v}{\textcolor{blue}{\underline{enc83\_tb.v}}}~~~

\end{frame}
%------------------------------------------------ SLIDE -
\section{8 入力~3 出力エンコーダ~(波形)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\vspace{-5mm}
\begin{verbatim}
% iverilog -Wall -o enc83 enc83_tb.v enc83.v
% ./enc83
% gtkwave enc83.vcd
\end{verbatim}

\vspace{2mm}
\includegraphics[width=\textwidth]{figs/enc83_vcd_crop.png}

\vspace{5mm}
\mbox{}問題: $d=0000000\textcolor{red}{0}$, $n=\textcolor{blue}{000}$;

\mbox{}\phantom{問題: }$d=0000000\textcolor{red}{1}$, $n=\textcolor{blue}{000}$。区別できない。

\end{frame}
%------------------------------------------------ SLIDE -
\section{エンコーダ~(論理式)}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{12}\selectfont
$n\mbox{[}0\mbox{]}=d\mbox{[}1\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}7\mbox{]}$

\vspace{1mm}
$n\mbox{[}1\mbox{]}=d\mbox{[}2\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}$

\vspace{1mm}
$n\mbox{[}2\mbox{]}=d\mbox{[}4\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}$

\vspace{1mm}
\textcolor{red}{
$r=d\mbox{[}0\mbox{]}+d\mbox{[}1\mbox{]}+d\mbox{[}2\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}4\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}$
}

\vspace{3.9mm}
\fontsize{12pt}{14.3}\selectfont
\setlength{\tabcolsep}{1.8pt}
\begin{tabular}{ccccccccccccc}\hline
\multicolumn{8}{c}{\rule{0pt}{.8\normalbaselineskip}入力\textcolor{red}{（制限あり）}}&&\multicolumn{4}{c}{出力}\\\cline{1-8}\cline{10-13}
\rule{0pt}{.8\normalbaselineskip}d[7]&d[6]&d[5]&d[4]&d[3]&d[2]&d[1]&d[0]&&n[2]&n[1]&n[0]&\red r\\\cline{1-8}\cline{10-13}
\rule{0pt}{.8\normalbaselineskip}%
 0 & 0 & 0 & 0 & 0 & 0 & 0 &     0 && 0 & 0 & 0 &\red 0\\[-3pt]
 0 & 0 & 0 & 0 & 0 & 0 & 0 &\red 1 && 0 & 0 & 0 &\red 1\\[-3pt]
 0 & 0 & 0 & 0 & 0 & 0 &\red 1 & 0 && 0 & 0 & 1 &\red 1\\[-3pt]
 0 & 0 & 0 & 0 & 0 &\red 1 & 0 & 0 && 0 & 1 & 0 &\red 1\\[-3pt]
 0 & 0 & 0 & 0 &\red 1 & 0 & 0 & 0 && 0 & 1 & 1 &\red 1\\[-3pt]
 0 & 0 & 0 &\red 1 & 0 & 0 & 0 & 0 && 1 & 0 & 0 &\red 1\\[-3pt]
 0 & 0 &\red 1 & 0 & 0 & 0 & 0 & 0 && 1 & 0 & 1 &\red 1\\[-3pt]
 0 &\red 1 & 0 & 0 & 0 & 0 & 0 & 0 && 1 & 1 & 0 &\red 1\\[-3pt]
\red 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 && 1 & 1 & 1 &\red 1\\\hline
\end{tabular}
\end{frame}
%------------------------------------------------ SLIDE -
\section{エンコーダ~(回路)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{12}\selectfont
$n\mbox{[}0\mbox{]}=d\mbox{[}1\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}7\mbox{]}$

\vspace{1mm}
$n\mbox{[}1\mbox{]}=d\mbox{[}2\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}$

\vspace{1mm}
$n\mbox{[}2\mbox{]}=d\mbox{[}4\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}$

\vspace{1mm}
\textcolor{red}{
$r=d\mbox{[}0\mbox{]}+d\mbox{[}1\mbox{]}+d\mbox{[}2\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}4\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}$
}

\vspace{2.47mm}
\begin{code}
`timescale 1ns/1ns
module enc83r (d, n, r);
    input  [7:0] d;
    output [2:0] n;
    output       r;
    assign n[0] = d[1] | d[3] | d[5] | d[7];
    assign n[1] = d[2] | d[3] | d[6] | d[7];
    assign n[2] = d[4] | d[5] | d[6] | d[7];
    assign r    = d[0] | d[1] | d[2] | d[3] |
                  d[4] | d[5] | d[6] | d[7];
endmodule
\end{code}

\vspace{-9mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/enc83r.v}{\color{blue}\underline{enc83r.v}}~~~

\end{frame}
%------------------------------------------------ SLIDE -
\section{エンコーダ~(テストベンチ)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\fontsize{8pt}{8.5}\selectfont
\begin{code}
`timescale 1ns/1ns
module enc83r_tb;
    reg  [7:0] d;
    wire [2:0] n;
    wire       r;
    enc83r i0 (d, n, r);
    initial begin
        #0 d = 8'b00000000;
        #1 d = 8'b00000001;
        #1 d = 8'b00000010;
        #1 d = 8'b00000100;
        #1 d = 8'b00001000;
        #1 d = 8'b00010000;
        #1 d = 8'b00100000;
        #1 d = 8'b01000000;
        #1 d = 8'b10000000;
        #1 $finish;
    end
    initial begin
        $dumpfile ("enc83r.vcd");
        $dumpvars;
    end
endmodule
\end{code}

\vspace{-8mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/enc83r_tb.v}{\textcolor{blue}{\underline{enc83r\_tb.v}}}~~~

\end{frame}
%------------------------------------------------ SLIDE -
\section{エンコーダ~(波形)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\vspace{-5mm}
\begin{verbatim}
% iverilog -Wall -o enc83r enc83r_tb.v enc83r.v
% ./enc83r
% gtkwave enc83r.vcd
\end{verbatim}

\vspace{2mm}
\includegraphics[width=\textwidth]{figs/enc83r_vcd_crop.png}

\vspace{2mm}
$d=0000000\textcolor{red}{0}$, $n=\textcolor{blue}{000}$, \textcolor{red}{$r=0$};

$d=0000000\textcolor{red}{1}$, $n=\textcolor{blue}{000}$, \textcolor{red}{$r=1$}。区別できる。

\end{frame}
%------------------------------------------------ SLIDE -
\section{イネーブル付きエンコーダ}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{12}\selectfont
$n\mbox{[}0\mbox{]}=\textcolor{red}e \mbox{(}d\mbox{[}1\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}7\mbox{]}\mbox{)}$

\vspace{1mm}
$n\mbox{[}1\mbox{]}=\textcolor{red}e \mbox{(}d\mbox{[}2\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}\mbox{)}$

\vspace{1mm}
$n\mbox{[}2\mbox{]}=\textcolor{red}e \mbox{(}d\mbox{[}4\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}\mbox{)}$

\vspace{1mm}
$r=\textcolor{red}e \mbox{(}d\mbox{[}0\mbox{]}+d\mbox{[}1\mbox{]}+d\mbox{[}2\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}4\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}\mbox{)}$

\vspace{3.7mm}
\fontsize{12pt}{14.3}\selectfont
\setlength{\tabcolsep}{1.5pt}
\begin{tabular}{cccccccccccccc}\hline
\multicolumn{9}{c}{\rule{0pt}{.8\normalbaselineskip}入力\textcolor{red}{（制限あり）}}&&\multicolumn{4}{c}{出力}\\\cline{1-9}\cline{11-14}
\rule{0pt}{.8\normalbaselineskip}\red e&d[7]&d[6]&d[5]&d[4]&d[3]&d[2]&d[1]&d[0]&&n[2]&n[1]&n[0]&r\\\cline{1-9}\cline{11-14}
\rule{0pt}{.8\normalbaselineskip}%
\red 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 &     0 && 0 & 0 & 0 & 0\\[-4pt]
\red 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 &\red 1 && 0 & 0 & 0 & 1\\[-4pt]
\red 1 & 0 & 0 & 0 & 0 & 0 & 0 &\red 1 & 0 && 0 & 0 & 1 & 1\\[-4pt]
\red 1 & 0 & 0 & 0 & 0 & 0 &\red 1 & 0 & 0 && 0 & 1 & 0 & 1\\[-4pt]
\red 1 & 0 & 0 & 0 & 0 &\red 1 & 0 & 0 & 0 && 0 & 1 & 1 & 1\\[-4pt]
\red 1 & 0 & 0 & 0 &\red 1 & 0 & 0 & 0 & 0 && 1 & 0 & 0 & 1\\[-4pt]
\red 1 & 0 & 0 &\red 1 & 0 & 0 & 0 & 0 & 0 && 1 & 0 & 1 & 1\\[-4pt]
\red 1 & 0 &\red 1 & 0 & 0 & 0 & 0 & 0 & 0 && 1 & 1 & 0 & 1\\[-4pt]
\red 1 &\red 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 && 1 & 1 & 1 & 1\\[-4pt]
\red 0 &\red x &\red x &\red x &\red x &\red x &\red x &\red x &\red x && 0 & 0 & 0 & 0\\\hline
\end{tabular}
\end{frame}
%------------------------------------------------ SLIDE -
\section{イネーブル付きエンコーダ~(回路)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{12}\selectfont
$n\mbox{[}0\mbox{]}=\textcolor{red}e \mbox{(}d\mbox{[}1\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}7\mbox{]}\mbox{)}$

\vspace{1mm}
$n\mbox{[}1\mbox{]}=\textcolor{red}e \mbox{(}d\mbox{[}2\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}\mbox{)}$

\vspace{1mm}
$n\mbox{[}2\mbox{]}=\textcolor{red}e \mbox{(}d\mbox{[}4\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}\mbox{)}$

\vspace{1mm}
$r=\textcolor{red}e \mbox{(}d\mbox{[}0\mbox{]}+d\mbox{[}1\mbox{]}+d\mbox{[}2\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}4\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}7\mbox{]}\mbox{)}$

\vspace{2.47mm}
\fontsize{11pt}{11.14}\selectfont
\begin{code}
`timescale 1ns/1ns
module enc83e (d, e, n, r);
    input  [7:0] d;
    input        e;
    output [2:0] n;
    output       r;
    assign n[0] = e & (d[1] | d[3] | d[5] | d[7]);
    assign n[1] = e & (d[2] | d[3] | d[6] | d[7]);
    assign n[2] = e & (d[4] | d[5] | d[6] | d[7]);
    assign r    = e & (d[0] | d[1] | d[2] | d[3] |
                       d[4] | d[5] | d[6] | d[7]);
endmodule
\end{code}

\vspace{-8mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/enc83e.v}{\color{blue}\underline{enc83e.v}}~~

\end{frame}
%------------------------------------------------ SLIDE -
\section{イネーブル付きエンコーダ~(テスト)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\vspace{-1mm}
\fontsize{8pt}{8}\selectfont
\begin{code}
`timescale 1ns/1ns
module enc83e_tb;
    reg  [7:0] d;
    reg        e;
    wire [2:0] n;
    wire       r;
    enc83e i0 (d, e, n, r);
    initial begin
        #0 d = 8'b00000000; e = 1;
        #1 d = 8'b00000001;
        #1 d = 8'b00000010;
        #1 d = 8'b00000100;
        #1 d = 8'b00001000;
        #1 d = 8'b00010000;
        #1 d = 8'b00100000;
        #1 d = 8'b01000000;
        #1 d = 8'b10000000;
        #1 d = 8'bxxxxxxxx; e = 0;
        #1 $finish;
    end
    initial begin
        $dumpfile ("enc83e.vcd");
        $dumpvars;
    end
endmodule
\end{code}

\vspace{-8mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/enc83e_tb.v}{\textcolor{blue}{\underline{enc83e\_tb.v}}}~~~

\end{frame}
%------------------------------------------------ SLIDE -
\section{イネーブル付きエンコーダ~(波形)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\vspace{-5mm}
\begin{verbatim}
% iverilog -Wall -o enc83e enc83e_tb.v enc83e.v
% ./enc83e
% gtkwave enc83e.vcd
\end{verbatim}

\vspace{2mm}
\includegraphics[width=\textwidth]{figs/enc83e_vcd_crop.png}

\end{frame}
%------------------------------------------------ SLIDE -
\section{プライオリティエンコーダ}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\renewcommand{\arraystretch}{1.06}
\fontsize{11pt}{13}\selectfont
\setlength{\tabcolsep}{2pt}
\begin{tabular}{cccccccccccccc}\hline
\multicolumn{9}{c}{\rule{0pt}{.8\normalbaselineskip}入力\textcolor{red}{（制限なし）}}&&\multicolumn{4}{c}{出力}\\\cline{1-9}\cline{11-14}
 ~\rule{0pt}{.8\normalbaselineskip}e~&d[7]&d[6]&d[5]&d[4]&d[3]&d[2]&d[1]&d[0]&&n[2]&n[1]&n[0]&~r~\\\cline{1-9}\cline{11-14}
\rule{0pt}{.8\normalbaselineskip}%
 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 &     0 && 0 & 0 & 0 & 0\\[-4pt]
 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 &\red 1 && 0 & 0 & 0 & 1\\[-4pt]
 1 & 0 & 0 & 0 & 0 & 0 & 0 &\red 1 &\blue x && 0 & 0 & 1 & 1\\[-4pt]
 1 & 0 & 0 & 0 & 0 & 0 &\red 1 &\blue x &\blue x && 0 & 1 & 0 & 1\\[-4pt]
 1 & 0 & 0 & 0 & 0 &\red 1 &\blue x &\blue x &\blue x && 0 & 1 & 1 & 1\\[-4pt]
 1 & 0 & 0 & 0 &\red 1 &\blue x &\blue x &\blue x &\blue x && 1 & 0 & 0 & 1\\[-4pt]
 1 & 0 & 0 &\red 1 &\blue x &\blue x &\blue x &\blue x &\blue x && 1 & 0 & 1 & 1\\[-4pt]
 1 & 0 &\red 1 &\blue x &\blue x &\blue x &\blue x &\blue x &\blue x && 1 & 1 & 0 & 1\\[-4pt]
 1 &\red 1 &\blue x &\blue x &\blue x &\blue x &\blue x &\blue x &\blue x && 1 & 1 & 1 & 1\\[-4pt]
 0 &\blue x &\blue x &\blue x &\blue x &\blue x &\blue x &\blue x &\blue x && 0 & 0 & 0 & 0\\\hline
\end{tabular}

\fontsize{10pt}{13}\selectfont

\vspace{3mm}
\textcolor{blue}{\resizebox{1.01\textwidth}{!}{$d\mbox{[}7\mbox{]}$の優先順位(プライオリティ)は一番高い、$d\mbox{[}0\mbox{]}$の優先順位は一番低い}}

\vspace{1mm}
\begin{tabular}{rcl}
$n\mbox{[}2\mbox{]}$ & $=$ & $e \ \mbox{(}d\mbox{[}7\mbox{]} + \overline{d\mbox{[}7\mbox{]}} \ d\mbox{[}6\mbox{]} + \overline{d\mbox{[}7\mbox{]}} \ \overline{d\mbox{[}6\mbox{]}} \ d\mbox{[}5\mbox{]} + \overline{d\mbox{[}7\mbox{]}} \ \overline{d\mbox{[}6\mbox{]}} \ \overline{d\mbox{[}5\mbox{]}} \ d\mbox{[}4\mbox{]}\mbox{)}$\\
         & $=$ & $e \ \mbox{(}d\mbox{[}7\mbox{]} + d\mbox{[}6\mbox{]} + \overline{d\mbox{[}6\mbox{]}} \ d\mbox{[}5\mbox{]} + \overline{d\mbox{[}6\mbox{]}} \ \overline{d\mbox{[}5\mbox{]}} \ d\mbox{[}4\mbox{]}\mbox{)}$\\
         & $=$ & $e \ \mbox{(}d\mbox{[}7\mbox{]} + d\mbox{[}6\mbox{]} + d\mbox{[}5\mbox{]} + \overline{d\mbox{[}5\mbox{]}} \ d\mbox{[}4\mbox{]}\mbox{)}$\\[0pt]
         & $=$ & $e \ \mbox{(}d\mbox{[}7\mbox{]} + d\mbox{[}6\mbox{]} + d\mbox{[}5\mbox{]} + d\mbox{[}4\mbox{]}\mbox{)}$  ~~~~~~~~~~\blue 第三回講義資料P27を参照\\
\end{tabular}
\end{frame}
%------------------------------------------------ SLIDE -
\section{プライオリティエンコーダ~(回路)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{12}\selectfont
$n\mbox{[}2\mbox{]}=e \ \mbox{(}d\mbox{[}7\mbox{]} + d\mbox{[}6\mbox{]} + d\mbox{[}5\mbox{]} + d\mbox{[}4\mbox{]}\mbox{)}$\\

\vspace{1mm}
$n\mbox{[}1\mbox{]}=e \ \mbox{(}
\boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} 
\mbox{)}$

\vspace{1mm}
$n\mbox{[}0\mbox{]}=e \ \mbox{(}
\boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} 
\mbox{)}$

\vspace{1mm}
$r=e \ \mbox{(}d\mbox{[}7\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}4\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}2\mbox{]}+d\mbox{[}1\mbox{]}+d\mbox{[}0\mbox{]}\mbox{)}$\\

\vspace{2.47mm}
\fontsize{10pt}{10.54}\selectfont
\begin{code}
`timescale 1ns/1ns
module enc83p (d, e, n, r);
    input  [7:0] d;
    input        e;
    output [2:0] n;
    output       r;
    assign n[2] = e & (d[7] | d[6] | d[5] | d[4]);
    assign n[1] = e & ( |  |  &  &  |  &  & );
    assign n[0] = e & ( |  &  |  &  &  |  &  &  & );
    assign r    = e & (d[7] | d[6] | d[5] | d[4] | 
                       d[3] | d[2] | d[1] | d[0]);
endmodule
\end{code}

\vspace{-8mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/enc83p.v}{\color{blue}\underline{enc83p.v}}~~

\end{frame}
%------------------------------------------------ SLIDE -
\section{プライオリティエンコーダ~(テスト)}
\begin{frame}[fragile]\frametitle{\secname}
\vspace{-1mm}
\fontsize{8pt}{8}\selectfont
\begin{code}
`timescale 1ns/1ns
module enc83p_tb;
    reg  [7:0] d;
    reg        e;
    wire [2:0] n;
    wire       r;
    enc83p i0 (d, e, n, r);
    initial begin
        #0 d = 8'b00000000; e = 1'b1;
        #1 d = 8'b00000001;
        #1 d = 8'b0000001x;
        #1 d = 8'b000001xx;
        #1 d = 8'b00001xxx;
        #1 d = 8'b0001xxxx;
        #1 d = 8'b001xxxxx;
        #1 d = 8'b01xxxxxx;
        #1 d = 8'b1xxxxxxx;
        #1 d = 8'bxxxxxxxx; e = 1'b0;
        #1 $finish;
    end
    initial begin
        $dumpfile ("enc83p.vcd");
        $dumpvars;
    end
endmodule
\end{code}

\vspace{-8mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/enc83p_tb.v}{\textcolor{blue}{\underline{enc83p\_tb.v}}}~~~

\end{frame}
%------------------------------------------------ SLIDE -
\section{プライオリティエンコーダ~(波形)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\vspace{-5mm}
\begin{verbatim}
% iverilog -Wall -o enc83p enc83p_tb.v enc83p.v
% ./enc83p
% gtkwave enc83p.vcd
\end{verbatim}

\vspace{2mm}
\includegraphics[width=\textwidth]{figs/enc83p_vcd_crop.png}

\end{frame}
%------------------------------------------------ SLIDE -
\section{プライオリティエンコーダ}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{14}\selectfont

入力制限なしの意味：任意の入力パターン

入力信号の数：9 （１本のeと８本のD（d[7:0]））

入力信号パターンの数：$2^9=512$

\vspace{3mm}
\setlength{\tabcolsep}{2.2pt}
\begin{tabular}{ccccccccccrr}\hline
\multicolumn{9}{c}{\rule{0pt}{.8\normalbaselineskip}入力\textcolor{red}{（制限なし）}}&&\multicolumn{2}{c}{パターンの数}\\\cline{1-9}\cline{11-12}
 \rule{0pt}{.8\normalbaselineskip}e&d[7]&d[6]&d[5]&d[4]&d[3]&d[2]&d[1]&d[0]&&\\\cline{1-9}\cline{11-12}
\rule{0pt}{.8\normalbaselineskip}%
 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 &     0 && &1\\[-4pt]
 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 &\red 1 && &1\\[-4pt]
 1 & 0 & 0 & 0 & 0 & 0 & 0 &\red 1 &\blue x && x {\footnotesize{が}} 1 {\footnotesize{個}} & 2\\[-4pt]
 1 & 0 & 0 & 0 & 0 & 0 &\red 1 &\blue x &\blue x && x {\footnotesize{が}} 2 {\footnotesize{個}} & 4\\[-4pt]
 1 & 0 & 0 & 0 & 0 &\red 1 &\blue x &\blue x &\blue x && x {\footnotesize{が}} 3 {\footnotesize{個}} & 8\\[-4pt]
 1 & 0 & 0 & 0 &\red 1 &\blue x &\blue x &\blue x &\blue x && x {\footnotesize{が}} 4 {\footnotesize{個}} & 16\\[-4pt]
 1 & 0 & 0 &\red 1 &\blue x &\blue x &\blue x &\blue x &\blue x && x {\footnotesize{が}} 5 {\footnotesize{個}} & 32\\[-4pt]
 1 & 0 &\red 1 &\blue x &\blue x &\blue x &\blue x &\blue x &\blue x && x {\footnotesize{が}} 6 {\footnotesize{個}} & 64\\[-4pt]
 1 &\red 1 &\blue x &\blue x &\blue x &\blue x &\blue x &\blue x &\blue x && x {\footnotesize{が}} 7 {\footnotesize{個}} & 128\\[-4pt]
 0 &\blue x &\blue x &\blue x &\blue x &\blue x &\blue x &\blue x &\blue x && x {\footnotesize{が}} 8 {\footnotesize{個}} & 256\\\hline
\end{tabular}

\vspace{3mm}
\resizebox{\textwidth}{!}{合計：$1+1+2+4+8+16+32+64+128+256=512=2^9$}
\end{frame}
%------------------------------------------------ SLIDE -
\section{エンコーダの応用 --- 割り込みコントローラ}
\begin{frame}\frametitle{\scalebox{.89}{\secname}}
割り込み (Interrupt) コントローラ (Controller)

\vspace{3mm}
\includegraphics[width=\textwidth]{figs/enc_interrupt.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{デコーダとエンコーダ}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}

  \textcolor{blue}{まとめ}

\vspace{3mm}
\begin{itemize}
\setlength{\itemsep}{2.6mm}
  \blue 
\item デコーダ (\textcolor{red}{$n \Rightarrow 2^n$})
\item イネーブル付きデコーダ
\item デマルチプレクサ

\vspace{13mm}
\item エンコーダ (\textcolor{red}{$2^n \Rightarrow n$})
\item イネーブル付きエンコーダ
\item プライオリティエンコーダ
\end{itemize}

\vspace{-70mm}
\hspace*{80mm}
\includegraphics[scale=.5]{figs/decoder.pdf}

\vspace{2mm}
\hspace*{80mm}
\includegraphics[scale=.5]{figs/encoder.pdf}

\end{frame}
%------------------------------------------------ SLIDE -
\section{課題~X (100 点)}
\begin{frame}\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{16}\selectfont
8 入力~3 出力プライオリティエンコーダを設計し動作検証シミュレーションして下さい（P37-P41を参照）。

\vspace{6mm}
$n\mbox{[}2\mbox{]}=e \ \mbox{(}d\mbox{[}7\mbox{]} + d\mbox{[}6\mbox{]} + d\mbox{[}5\mbox{]} + d\mbox{[}4\mbox{]}\mbox{)}$\\

\vspace{3.5mm}
$n\mbox{[}1\mbox{]}=e \ \mbox{(}
\boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} 
\mbox{)}$

\vspace{3mm}
$n\mbox{[}0\mbox{]}=e \ \mbox{(}
\boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} 
\mbox{)}$

\vspace{3mm}
$r=e \ \mbox{(}d\mbox{[}7\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}4\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}2\mbox{]}+d\mbox{[}1\mbox{]}+d\mbox{[}0\mbox{]}\mbox{)}$\\


\vspace{6.5mm}
モジュール名は~\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/enc83p.v}{\textcolor{blue}{\underline{enc83p}}} にすること。\\
テストベンチ~\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/enc83p_tb.v}{\textcolor{blue}{\underline{enc83p\_tb.v}}} を使って下さい。\\
真理値表からn[2]、n[1]、n[0]の導出過程を書いて下さい。

\vspace{-54mm}
\hspace*{82mm}
\includegraphics[width=.3\textwidth]{figs/enc83p.pdf}

\end{frame}
%------------------------------------------------ SLIDE -
\section{課題~X (100 点)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\fontsize{12pt}{12}\selectfont
$n\mbox{[}2\mbox{]}=e \ \mbox{(}d\mbox{[}7\mbox{]} + d\mbox{[}6\mbox{]} + d\mbox{[}5\mbox{]} + d\mbox{[}4\mbox{]}\mbox{)}$\\

\vspace{1mm}
$n\mbox{[}1\mbox{]}=e \ \mbox{(}
\boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} 
\mbox{)}$

\vspace{1mm}
$n\mbox{[}0\mbox{]}=e \ \mbox{(}
\boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} +
\boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} \ \boxed{\phantom{\overline{\cdot}}} 
\mbox{)}$

\vspace{1mm}
$r=e \ \mbox{(}d\mbox{[}7\mbox{]}+d\mbox{[}6\mbox{]}+d\mbox{[}5\mbox{]}+d\mbox{[}4\mbox{]}+d\mbox{[}3\mbox{]}+d\mbox{[}2\mbox{]}+d\mbox{[}1\mbox{]}+d\mbox{[}0\mbox{]}\mbox{)}$\\

\vspace{2.47mm}
\fontsize{10pt}{10.54}\selectfont
\begin{code}
`timescale 1ns/1ns
module enc83p (d, e, n, r);
    input  [7:0] d;
    input        e;
    output [2:0] n;
    output       r;
    assign n[2] = e & (d[7] | d[6] | d[5] | d[4]);
    assign n[1] = e & ( |  |  &  &  |  &  & );
    assign n[0] = e & ( |  &  |  &  &  |  &  &  & );
    assign r    = e & (d[7] | d[6] | d[5] | d[4] | 
                       d[3] | d[2] | d[1] | d[0]);
endmodule
\end{code}

\vspace{-8mm}
\hfill
\href{https://yamin.cis.k.hosei.ac.jp/lectures/logic/enc83p.v}{\color{blue}\underline{enc83p.v}}~~

\end{frame}
%------------------------------------------------ SLIDE -
\section{課題~X (100 点)}
\begin{frame}[fragile]\frametitle{\scalebox{.96}{\secname}}
\vspace{-5mm}
\begin{verbatim}
% iverilog -Wall -o enc83p enc83p_tb.v enc83p.v
% ./enc83p
% gtkwave enc83p.vcd
\end{verbatim}

\vspace{2mm}
\includegraphics[width=\textwidth]{figs/enc83p_vcd_crop.png}

\end{frame}
%------------------------------------------------ SLIDE -
\end{document}
%------------------------------------------------ SLIDE -
