\documentclass[dvipdfmx,t,serif,mathserif,14pt]{beamer} % t: from top; serif: rmdefault
\usepackage{mybeamer}
\usepackage{alltt}
\usepackage{rotating}
\usepackage[dvipdfmx]{animate}

\usepackage{mycolor}
\usepackage{contour}

\newcommand{\PDFTITLE}{コンピュータ構成と設計（９）}
\newcommand{\PDFSUBJECT}{二年生秋学期}
\newcommand{\PDFAUTHOR}{法政大学情報科学部}
\newcommand{\PDFKEYWORDS}{パイプライン CPU 設計}
\date{2023 年 11 月 23 日 (木)}

\title{\PDFTITLE} % bottom PDFTITLE
\subtitle{パイプライン CPU 設計}
\author[\PDFAUTHOR]{李　亜民} % bottom PDFAUTHOR; titlepage Yamin Li

\hypersetup{
  pdftitle=\PDFTITLE,
  pdfsubject=\PDFSUBJECT,
  pdfauthor=\PDFAUTHOR,
  pdfkeywords=\PDFKEYWORDS
}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{document}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\everymath={\rm}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{\PDFTITLE}
\begin{frame}
  \titlepage
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{コンピュータとコンピュータシステム}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/CompSys.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{20 RISC-V 命令のまとめ}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{9pt}{11pt}\selectfont
\vspace{-3mm}
\begin{verbatim}
 1. add  rd, rs1, rs2    # rd <- rs1 + rs2
 2. sub  rd, rs1, rs2    # rd <- rs1 - rs2
 3. slt  rd, rs1, rs2    # rd <- rs1 < rs2 (signed)
 4. xor  rd, rs1, rs2    # rd <- rs1 ^ rs2
 5. or   rd, rs1, rs2    # rd <- rs1 | rs2
 6. and  rd, rs1, rs2    # rd <- rs1 & rs2
 7. slli rd, rs1, shamt  # rd <- rs1 << shamt
 8. srli rd, rs1, shamt  # rd <- rs1 >> shamt
 9. srai rd, rs1, shamt  # rd <- rs1 >>>shamt
10. jalr rd, rs1, imm    # rd <- pc+4; pc <- rs1+imm
11. addi rd, rs1, imm    # rd <- rs1 + imm
12. xori rd, rs1, imm    # rd <- rs1 ^ imm
13. ori  rd, rs1, imm    # rd <- rs1 | imm
14. andi rd, rs1, imm    # rd <- rs1 & imm
15. lw   rd,  imm(rs1)   # rd <- memory[rs1+imm]
16. sw   rs2, imm(rs1)   # memory[rs1+imm] <- rs2
17. beq  rs1, rs2, label # if (rs1==rs2) pc <- label
18. bne  rs1, rs2, label # if (rs1!=rs2) pc <- label
19. jal  rd,  label      # rd <- pc+4;   pc <- label
20. lui  rd,  imm        # rd <- imm,000000000000
\end{verbatim}
\end{frame}
%------------------------------------------------ SLIDE -
\section{RV32I Base Instruction Set Encoding}
\begin{frame}\frametitle{\secname}
\fontsize{9pt}{10.6}\selectfont
\begin{tabular}{p{1in}p{0.1in}p{0.1in}p{0.1in}p{0.1in}p{0.1in}p{0.8in}p{0.8in}p{1.5in}p{1in}rl}
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} &1.& add \\
\cline{1-10}
\multicolumn{4}{|c|}{0100000} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} &2.& sub \\
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{010} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} &3.& slt \\
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{100} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} &4.& xor \\
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{110} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} &5.& or \\
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{111} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} &6.& and \\
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{\blue shamt} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{001} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &7.& slli \\
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{\blue shamt} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{101} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &8.& srli \\
\cline{1-10}
\multicolumn{4}{|c|}{0100000} &
\multicolumn{2}{c|}{\blue shamt} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{101} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &9.& srai \\
\cline{1-10}
\multicolumn{6}{|c|}{\blue imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{1100111} &10.& jalr \\
\cline{1-10}
\multicolumn{6}{|c|}{\blue imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &11.& addi \\
\cline{1-10}
\multicolumn{6}{|c|}{\blue imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{100} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &12.& xori \\
\cline{1-10}
\multicolumn{6}{|c|}{\blue imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{110} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &13.& ori \\
\cline{1-10}
\multicolumn{6}{|c|}{\blue imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{111} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &14.& andi \\
\cline{1-10}
\multicolumn{6}{|c|}{\blue imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{010} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0000011} &15.& lw \\
\cline{1-10}
\multicolumn{4}{|c|}{\blue imm[11:5]} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{010} &
\multicolumn{1}{c|}{\blue imm[4:0]} &
\multicolumn{1}{c|}{0100011} &16.& sw \\
\cline{1-10}
\multicolumn{4}{|c|}{\blue imm[12$\vert$10:5]} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{\blue imm[4:1$\vert$11]} &
\multicolumn{1}{c|}{1100011} &17.& beq \\
\cline{1-10}
\multicolumn{4}{|c|}{\blue imm[12$\vert$10:5]} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{001} &
\multicolumn{1}{c|}{\blue imm[4:1$\vert$11]} &
\multicolumn{1}{c|}{1100011} &18.& bne \\
\cline{1-10}
\multicolumn{8}{|c|}{\blue imm[20$\vert$10:1$\vert$11$\vert$19:12]} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{1101111} &19.& jal \\
\cline{1-10}
\multicolumn{8}{|c|}{\blue imm[31:12]} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110111} &~~~~20.& lui \\
\cline{1-10}

\end{tabular}
\end{frame}
%------------------------------------------------ SLIDE -
\section{周波数と一サイクルの時間の関係}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/cycle_frequency.pdf}
\fontsize{12pt}{13}\selectfont

\vspace{1mm}
\renewcommand{\arraystretch}{2.4}
\setlength\tabcolsep{3pt}
\begin{tabular}{ll}
周波数~$F=$~\textcolor{red}{1}GHz: & 一周期の時間~$T=$~$\displaystyle \frac{1}{\textcolor{red}{1} \times 10^9}=10^{-9}$s~$=$~1ns\\
周波数~$F=$~\textcolor{red}{1}MHz: & 一周期の時間~$T=$~$\displaystyle \frac{1}{\textcolor{red}{1} \times 10^6}=10^{-6}$s~$=$~1$\mu$s\\
周波数~$F=$~\textcolor{red}{1}kHz: & 一周期の時間~$T=$~$\displaystyle \frac{1}{\textcolor{red}{1} \times 10^3}=10^{-3}$s~$=$~1ms\\
周波数~$F=$~\textcolor{red}{1}Hz:  & 一周期の時間~$T=$~$\displaystyle \frac{1}{\textcolor{red}{1} \times 10^0}=10^{-0}$s~$=$~~1s (秒)
\end{tabular}

\end{frame}
%------------------------------------------------ SLIDE -
\section{パイプライン方式}
\begin{frame}[fragile]\frametitle{\secname}
\animategraphics[width=\textwidth,autoplay,loop]{5}{figs/anim+}{8}{8}

\vspace{4mm}\LARGE
せーのっ !!!
\end{frame}
%------------------------------------------------ SLIDE -
\section{パイプライン方式}
\begin{frame}[fragile]\frametitle{\secname}
\animategraphics[width=\textwidth,autoplay,loop]{5}{figs/anim+}{1}{7}

\vspace{4mm}\LARGE
Display this PDF with Adobe Acrobat Reader DC
\end{frame}
%------------------------------------------------ SLIDE -
\section{パイプライン方式}
\begin{frame}[fragile]\frametitle{\secname}
\animategraphics[width=\textwidth,autoplay,loop]{5}{figs/anim+}{8}{8}

\vspace{4mm}\LARGE
Display this PDF with Adobe Acrobat Reader DC
\end{frame}
%------------------------------------------------ SLIDE -
\section{パイプラインの概念}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=1.27\textwidth]{figs/3cpu_timing.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{簡略化したパイプライン CPU 回路}
\begin{frame}[fragile]\frametitle{\secname}
\begin{animateinline}[autoplay]{1}
\includegraphics[width=\textwidth]{figs/pipanim00.pdf}
\end{animateinline}

\end{frame}
%------------------------------------------------ SLIDE -
\section{パイプライン方式で命令を実行}
\begin{frame}[fragile]\frametitle{\secname}
\begin{animateinline}[autoplay]{1}
\includegraphics[width=\textwidth]{figs/pipanim01.pdf}
\end{animateinline}

\vspace{-30mm}
\hspace*{35mm}
Display this PDF with 

\hspace*{35mm}
Adobe Acrobat Reader DC

\end{frame}
%------------------------------------------------ SLIDE -
% revise ~/bin/replace-year-pipanim
% sh pipanim-change-years-2023.sh
%------------------------------------------------ SLIDE -
\section{パイプライン方式で命令を実行}
\begin{frame}[fragile]\frametitle{\secname}
\begin{animateinline}[autoplay]{1}
         \includegraphics[width=\textwidth]{figs/pipanim01.pdf}
\newframe\includegraphics[width=\textwidth]{figs/pipanim02.pdf}
\newframe\includegraphics[width=\textwidth]{figs/pipanim03.pdf}
\newframe\includegraphics[width=\textwidth]{figs/pipanim04.pdf}
\newframe\includegraphics[width=\textwidth]{figs/pipanim05.pdf}
\newframe\includegraphics[width=\textwidth]{figs/pipanim06.pdf}
\newframe\includegraphics[width=\textwidth]{figs/pipanim07.pdf}
\newframe\includegraphics[width=\textwidth]{figs/pipanim08.pdf}
\newframe\includegraphics[width=\textwidth]{figs/pipanim09.pdf}
\newframe\includegraphics[width=\textwidth]{figs/pipanim10.pdf}
\newframe\includegraphics[width=\textwidth]{figs/pipanim11.pdf}
\newframe\includegraphics[width=\textwidth]{figs/pipanim12.pdf}
\newframe\includegraphics[width=\textwidth]{figs/pipanim13.pdf}
\end{animateinline}

\end{frame}
%------------------------------------------------ SLIDE -
\section{パイプライン方式で命令を実行}
\begin{frame}[fragile]\frametitle{\secname}
\begin{animateinline}[autoplay]{1}
\includegraphics[width=\textwidth]{figs/pipanim13.pdf}
\end{animateinline}

\end{frame}
%------------------------------------------------ SLIDE -
\section{単一サイクル CPU 回路}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/sc_computer.pdf}

\vspace{4mm}
CPU $+$ 命令メモリ Imem $+$ データメモリ Dmem
\end{frame}
%------------------------------------------------ SLIDE -
\section{単一サイクル CPU 回路}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_pipe_not.pdf}

\vspace{1mm}
同じものである
\end{frame}
%------------------------------------------------ SLIDE -
\section{単一サイクル CPU 回路}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_pipe_stages.pdf}

\vspace{1mm}
ステージに分割する
\end{frame}
%------------------------------------------------ SLIDE -
\section{パイプライン CPU 回路}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_pipe_regs.pdf}

\vspace{1mm}
ステージとステージの間にはレジスタを挿入する
\end{frame}
%------------------------------------------------ SLIDE -
\section{パイプラインハザードの種類}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{11pt}{12}\selectfont
{\darkmagenta ハザード~~~---~~~命令ストリームにある次の命令を想定されたクロック・サイクル中に実行することを妨げる状況が存在する}

\vspace{5mm}
\begin{enumerate}
\setlength{\itemsep}{5mm}
\item 構造ハザード (Structural Hazard): 
    {\darkgreen\begin{itemize}
    \item ハードウェア資源の競合によって起こる。資源の競合とは同時多重実行されうる複数の命令が同じハードウェア資源を要求したため，システムがその要求を満たせない状態である
    \end{itemize}}
\item 制御ハザード (Control Hazard): 
    {\darkgreen\begin{itemize}
    \item 分岐命令や割り込みなどパイプラインの流れを変えてしまうことによって発生する
    \end{itemize}}
\item データハザード (Data Hazard): 
    {\darkgreen\begin{itemize}
    \item 命令が直前の命令の実行結果を使用している時に発生する
    \end{itemize}}
\end{enumerate}
\end{frame}
%------------------------------------------------ SLIDE -
\section{パイプラインハザードの解消方法}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{11pt}{12}\selectfont
{\darkmagenta ハザード~~~---~~~命令ストリームにある次の命令を想定されたクロック・サイクル中に実行することを妨げる状況が存在する}

\vspace{5mm}
\begin{enumerate}
\setlength{\itemsep}{5mm}
\item 構造ハザード (Structural Hazard): 
    {\darkgreen\begin{itemize}
    \item 複数のアクセスに対応したハードウェア資源を採用する
    \item コンパイラによるスケジューリング
    \end{itemize}}
\item 制御ハザード (Control Hazard): 
    {\darkgreen\begin{itemize}
    \item 遅延分岐
    \item 分岐予測機構による投機実行 
    \end{itemize}}
\item データハザード (Data Hazard): 
    {\darkgreen\begin{itemize}
    \item コンパイラによるスケジューリング
    \item フォアワーディング (バイパスを設ける)
    \end{itemize}}
\end{enumerate}
\end{frame}
%------------------------------------------------ SLIDE -
\section{Jump: Cancel the Next Instruction}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/jump.pdf}

\vspace{5mm}
Unconditional jump
\end{frame}
%------------------------------------------------ SLIDE -
\section{Branch: Cancel the Next Instruction}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/branch_taken.pdf}

\vspace{5mm}
Conditional branch: Branch is taken
\end{frame}
%------------------------------------------------ SLIDE -
\section{Branch is not Taken: Do not Cancel}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/branch_not_taken.pdf}

\vspace{5mm}
Conditional branch: Branch is not taken
\end{frame}
%------------------------------------------------ SLIDE -
\section{データハザード (Data Hazard)}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics{figs/data_hazard_add_sub.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{フォアワーディング (Forwarding)}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics{figs/data_hazard_add_sub_forward.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{フォアワーディング  --- from add}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/forward_to_sub.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{フォアワーディング  --- from lw}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/forward_from_lw.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{フォアワーディング --- fwda}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{11pt}{16}\selectfont
\begin{code}
fwda = 2'b00; // default: no hazards
if (ewreg & (erd != 0) & (erd == rs1) & ~em2reg) begin
    fwda = 2'b01; // select exe_alu
end else begin
    if (mwreg & (mrd != 0) & (mrd == rs1) & ~mm2reg) begin
        fwda = 2'b10; // select mem_alu
    end else begin
        if (mwreg & (mrd != 0) & (mrd == rs1) & mm2reg) begin
            fwda = 2'b11; // select mem_lw
        end
    end
end
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{フォアワーディング --- fwdb}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{11pt}{16}\selectfont
\begin{code}
fwdb = 2'b00; // default: no hazards
if (ewreg & (erd != 0) & (erd == rs2) & ~em2reg) begin
    fwdb = 2'b01; // select exe_alu
end else begin
    if (mwreg & (mrd != 0) & (mrd == rs2) & ~mm2reg) begin
        fwdb = 2'b10; // select mem_alu
    end else begin
        if (mwreg & (mrd != 0) & (mrd == rs2) & mm2reg) begin
            fwdb = 2'b11; // select mem_lw
        end
    end
end
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{lwは次の命令にデータを転送できない}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics{figs/lw_cannot_forward.pdf}

\vspace{6mm}
ロード(lw)命令はand命令には結果を転送できるが，sub命令にはできない。なぜなら，sub命令がデータを必要とするときがロード命令の結果が得られたときよりも{\darkgreen{``時間的に前''}}だからである
\end{frame}
%------------------------------------------------ SLIDE -
\section{パイプライン・ストールを起こす}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics{figs/lw_stall.pdf}

\vspace{6mm}
パイプラインをストール(Stall)させるために，PCとIDパイプライン・レジスタへの書き込みを防ぐ信号wpcirを生成する
\end{frame}
%------------------------------------------------ SLIDE -
\section{パイプライン・ストール --- wpcir}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{10pt}{11}\selectfont
\begin{code}
i_rs1 = i_jalr | i_beq  | i_bne  | i_lw   | i_sw   | i_addi |
        i_xori | i_ori  | i_andi | i_slli | i_srli | i_srai |
        i_add  | i_sub  | i_slt  | i_xor  | i_or   | i_and;

i_rs2 = i_beq  | i_bne  | i_sw   |
        i_add  | i_sub  | i_slt  | i_xor  | i_or   | i_and;

wpcir = ~(ewreg & em2reg & (erd != 0) &
         (i_rs1 & (erd == rs1) |
          i_rs2 & (erd == rs2)));

wreg = (i_lui  | i_jal  | i_jalr | i_lw   | i_addi | i_xori |
        i_ori  | i_andi | i_slli | i_srli | i_srai | i_add  |
        i_sub  | i_slt  | i_xor  | i_or   | i_and) & wpcir & ~ecancel;

wmem  = i_sw & wpcir & ~ecancel;
\end{code}

wpcir\,は\,0\,の時、PC\,と\,IR\,に書き込まない
\end{frame}
%------------------------------------------------ SLIDE -
\section{パイプライン CPU 回路}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_rv32i.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{pl\_computer.v}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{5pt}{5.6}\selectfont
\vspace{-2mm}
\begin{code}
module pl_computer (clk,clrn,pc,inst,eal,mal,wres);                     // pipelined cpu
    input         clk;             // clock                             // plus inst mem
    input         clrn;            // reset                             // and  data mem
    output [31:0] pc;              // program counter
    output [31:0] inst;            // instruction in ID stage
    output [31:0] eal;             // alu or epc4 in EXE stage
    output [31:0] mal;             // eal in MEM stage
    output [31:0] wres;            // data to be written into register file

    // signals in IF stage
    wire   [31:0] pc4;             // pc+4 in IF stage
    wire   [31:0] ins;             // instruction in IF stage
    wire   [31:0] npc;             // next pc in IF stage
    // signals in ID stage
    wire   [31:0] dpc;             // pc in ID stage
    wire   [31:0] dpc4;            // pc+4 in ID stage
    wire   [31:0] bra;             // branch target of beq and bne instructions
    wire   [31:0] jalra;           // jump target of jalr instruction
    wire   [31:0] jala;            // jump target of jal instruction
    wire   [31:0] da;              // operand a in ID stage
    wire   [31:0] db;              // operand b in ID stage
    wire   [31:0] dd;              // reg data to mem in ID stage
    wire    [4:0] rd = inst[11:7]; // destination register number in ID stage
    wire    [3:0] aluc;            // alu control in ID stage
    wire    [1:0] pcsrc;           // next pc (npc) select in ID stage
    wire          wpcir;           // pipepc and pipeir write enable
    wire          m2reg;           // memory to register in ID stage
    wire          wreg;            // register file write enable in ID stage
    wire          wmem;            // memory write in ID stage
    wire          call;            // jalr, jal in ID stage
    wire          cancel;          // cancel in ID stage
    // signals in EXE stage
    wire   [31:0] epc4;            // pc+4 in EXE stage
    wire   [31:0] ea;              // operand a in EXE stage
    wire   [31:0] eb;              // operand b in EXE stage
    wire   [31:0] ed;              // reg data to mem in EXE stage
    wire    [4:0] erd;             // destination register number in EXE stage
    wire    [3:0] ealuc;           // alu control in EXE stage
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{pl\_computer.v}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{5pt}{5.6}\selectfont
\vspace{-2mm}
\begin{code}
    wire          em2reg;          // memory to register in EXE stage
    wire          ewreg;           // register file write enable in EXE stage
    wire          ewmem;           // memory write in EXE stage
    wire          ecall;           // jalr, jal in EXE stage
    wire          ecancel;         // cancel in EXE stage
    // signals in MEM stage
    wire   [31:0] mm;              // memory data out in MEM stage
    wire   [31:0] md;              // reg data to mem in MEM stage
    wire    [4:0] mrd;             // destination register number in MEM stage
    wire          mm2reg;          // memory to register in MEM stage
    wire          mwreg;           // register file write enable in MEM stage
    wire          mwmem;           // memory write in MEM stage
    // signals in WB stage
    wire   [31:0] wal;             // mal in WB stage
    wire   [31:0] wm;              // memory data out in WB stage
    wire    [4:0] wrd;             // destination register number in WB stage
    wire          wm2reg;          // memory to register in WB stage
    wire          wwreg;           // register file write enable in WB stage
    // program counter
    pl_reg_pc prog_cnt (npc,wpcir,clk,clrn, pc);
    pl_stage_if if_stage (pcsrc,pc,bra,jalra,jala,npc,pc4,ins);             // IF stage
    // IF/ID pipeline register
    pl_reg_ir fd_reg ( pc, pc4,ins, wpcir,clk,clrn, dpc,dpc4,inst);
    pl_stage_id id_stage (mrd,mm2reg,mwreg,erd,em2reg,ewreg,ecancel,dpc,inst,eal,mal,mm,
                          wrd,wres,wwreg,clk,clrn,bra,jalra,jala,pcsrc,wpcir,cancel,wreg,
                          m2reg,wmem,call,aluc,da,db,dd);                   // ID stage
    // ID/EXE pipeline register
    pl_reg_de de_reg ( cancel, wreg, m2reg, wmem, call, aluc, rd,dpc4,da,db,dd,clk,clrn,
                      ecancel,ewreg,em2reg,ewmem,ecall,ealuc,erd,epc4,ea,eb,ed);
    pl_stage_exe exe_stage (ea,eb,epc4,ealuc,ecall, eal);                   // EXE stage
    // EXE/MEM pipeline register
    pl_reg_em em_reg (ewreg,em2reg,ewmem,eal,ed,erd,clk,clrn,
                      mwreg,mm2reg,mwmem,mal,md,mrd);
    pl_stage_mem mem_stage (mwmem,mal,md,clk, mm);                          // MEM stage
    // MEM/WB pipeline register
    pl_reg_mw mw_reg (mwreg,mm2reg,mm,mal,mrd,clk,clrn,wwreg,wm2reg,wm,wal,wrd);
    pl_stage_wb wb_stage (wal,wm,wm2reg, wres);                             // WB stage
endmodule
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{命令メモリ (テスト・プログラム)}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{5pt}{5.6}\selectfont
\vspace{-2mm}
\begin{code}
module pl_instmem (a,inst);
    input  [31:0] a;
    output [31:0] inst;
    wire   [31:0] rom [0:31];                                 // (pc)
    assign rom[5'h00] = 32'b00000000000000000000000010110111; // (00) main:   lui  x1, 0         # x1 <- 0
    assign rom[5'h01] = 32'b00000101000000001110001000010011; // (04)         ori  x4, x1, 80    # x1 <- 80
    assign rom[5'h02] = 32'b00000000010000000000001010010011; // (08)         addi x5, x0,  4    # x5 <- 4
    assign rom[5'h03] = 32'b00000101100000000000000011101111; // (0c) call:   jal  x1, sum       # x1 <- 0x10 (return address), call sum
    assign rom[5'h04] = 32'b00000000011000100010000000100011; // (10)         sw   x6, 0(x4)     # memory[x4+0] <- x6
    assign rom[5'h05] = 32'b00000000000000100010010010000011; // (14)         lw   x9, 0(x4)     # x6 <- memory[x4+0]
    assign rom[5'h06] = 32'b01000000010001001000010000110011; // (18)         sub  x8, x9, x4    # x8 <- x9 - x4, pipeline stall
    assign rom[5'h07] = 32'b00000000001100000000001010010011; // (1c)         addi x5, x0,  3    # x5 <- 3
    assign rom[5'h08] = 32'b11111111111100101000001010010011; // (20) loop2:  addi x5, x5, -1    # x5 <- x5 - 1
    assign rom[5'h09] = 32'b11111111111100101110010000010011; // (24)         ori  x8, x5, 0xfff # x8 <- x5 | 0xffffffff = 0xffffffff
    assign rom[5'h0a] = 32'b01010101010101000100010000010011; // (28)         xori x8, x8, 0x555 # x8 <- x8 ^ 0x00000555 = 0xfffffaaa
    assign rom[5'h0b] = 32'b11111111111100000000010010010011; // (2c)         addi x9, x0, -1    # x9 <- 0xffffffff
    assign rom[5'h0c] = 32'b11111111111101001111010100010011; // (30)         andi x10,x9, 0xfff # x10<- x9 & 0xffffffff = 0xffffffff
    assign rom[5'h0d] = 32'b00000000100101010110001000110011; // (34)         or   x4, x10, x9   # x4 <- x10 | x9 = 0xffffffff
    assign rom[5'h0e] = 32'b00000000100101010100010000110011; // (38)         xor  x8, x10, x9   # x8 <- x10 ^ x9 = 0x00000000
    assign rom[5'h0f] = 32'b00000000010001010111001110110011; // (3c)         and  x7, x10, x4   # x7 <- x10 & x4 = 0xffffffff
    assign rom[5'h10] = 32'b00000000000000101000010001100011; // (40)         beq  x5, x0, shift # if x5 = 0, goto shift
    assign rom[5'h11] = 32'b11111101110111111111000001101111; // (44)         jal  x0, loop2     # jump loop2
    assign rom[5'h12] = 32'b11111111111100000000001010010011; // (48) shift:  addi x5, x0, -1    # x5 <- 0xffffffff
    assign rom[5'h13] = 32'b00000000111100101001010000010011; // (4c)         slli x8, x5, 15    # x8 <- 0xffffffff <<  15 = 0xffff8000
    assign rom[5'h14] = 32'b00000001000001000001010000010011; // (50)         slli x8, x8, 16    # x8 <- 0xffff8000 <<  16 = 0x80000000
    assign rom[5'h15] = 32'b01000001000001000101010000010011; // (54)         srai x8, x8, 16    # x8 <- 0x80000000 >>> 16 = 0xffff8000
    assign rom[5'h16] = 32'b00000000111101000101010000010011; // (58)         srli x8, x8, 15    # x8 <- 0xffff8000 >>  15 = 0x0001ffff
    assign rom[5'h17] = 32'b00000000011000100010000110110011; // (5c)         slt  x3, x4, x6    # x3 <- 0xffffffff < 0x000002ff = 1
    assign rom[5'h18] = 32'b00000000000000000000000001101111; // (60) finish: jal  x0, finish    # dead loop
    assign rom[5'h19] = 32'b00000000000000000000001100110011; // (64) sum:    add  x6, x0, x0    # x6 <- 0 (subroutine entry)
    assign rom[5'h1a] = 32'b00000000000000100010010010000011; // (68) loop:   lw   x9, 0(x4)     # x9 <- memory[x4+0]
    assign rom[5'h1b] = 32'b00000000010000100000001000010011; // (6c)         addi x4, x4,  4    # x4 <- x4 + 4 (address+4)
    assign rom[5'h1c] = 32'b00000000100100110000001100110011; // (70)         add  x6, x6, x9    # x6 <- x6 + x9 (sum)
    assign rom[5'h1d] = 32'b11111111111100101000001010010011; // (74)         addi x5, x5, -1    # x5 <- x5 - 1 (counter--)
    assign rom[5'h1e] = 32'b11111110000000101001100011100011; // (78)         bne  x5, x0, loop  # if x5 != 0, goto loop
    assign rom[5'h1f] = 32'b00000000000000001000000001100111; // (7c)         ret  x1            # return from subroutine
    assign inst = rom[a[6:2]];
endmodule
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{データメモリ (テスト・データ)}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{8pt}{9.672}\selectfont
\vspace{-2mm}
\begin{code}
module pl_datamem (addr,datain,we,clk,dataout); // data memory, ram
    input         clk;                          // clock
    input         we;                           // write enable
    input  [31:0] datain;                       // data in (to memory)
    input  [31:0] addr;                         // ram address
    output [31:0] dataout;                      // data out (from memory)
    reg    [31:0] ram [0:31];                   // ram cells: 32 words * 32 bits
    assign dataout = ram[addr[6:2]];            // use word address to read ram
    always @ (posedge clk)
        if (we) ram[addr[6:2]] = datain;        // use word address to write ram
    integer i;
    initial begin                               // initialize memory
        for (i = 0; i < 32; i = i + 1)
            ram[i] = 0;
        // ram[word_addr] = data                // (byte_addr) item in data array
        ram[5'h14] = 32'h000000f2;              // (50)  data[0]
        ram[5'h15] = 32'h0000000e;              // (54)  data[1]
        ram[5'h16] = 32'h00000200;              // (58)  data[2]
        ram[5'h17] = 32'hffffffff;              // (5c)  data[3]
        // ram[5'h18] the sum stored by sw instruction
    end
endmodule
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Registers}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave1_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(00) main:   lui  x1, 0                                (64) sum:    add  x6, x0, x0
(04)         ori  x4, x1, 80                           (68) loop:   lw   x9, 0(x4)
(08)         addi x5, x0,  4                           (6c)         addi x4, x4,  4
(0c) call:   jal  x1, sum                              (70)         add  x6, x6, x9
(10) canceled                                          (74)         addi x5, x5, -1
\end{code}


\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.7mm}%
\textcolor{cyan}{lui}~\hspace{3.155mm}%
ori~\hspace{3.155mm}%
addi\hspace{3.155mm}%
jal~\hspace{.8mm}%
\textcolor{red}{cancel}\hspace{2mm}%
add~\hspace{2.9mm}%
~lw~\hspace{3.155mm}%
addi\hspace{3.155mm}%
add~\hspace{3.mm}%
addi\hspace{3.155mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Registers}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave2_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(78)         bne  x5, x0, loop                         (74)         addi x5, x5, -1
(7c) canceled                                          (78)         bne  x5, x0, loop
(68) loop:   lw   x9, 0(x4)                            (7c) canceled
(6c)         addi x4, x4,  4                           (68) loop:   lw   x9, 0(x4)
(70)         add  x6, x6, x9                           (6c)         addi x4, x4,  4
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.7mm}%
\textcolor{cyan}{bne}~\hspace{.5mm}%
\textcolor{red}{cancel}\hspace{2mm}%
~lw~\hspace{3.155mm}%
addi\hspace{3.155mm}\hspace{.2mm}%
add~\hspace{3.155mm}%
addi\hspace{3.155mm}\hspace{.5mm}%
bne~\hspace{.5mm}%
\textcolor{red}{cancel}\hspace{1.49mm}%
~lw~\hspace{3.155mm}%
addi\hspace{3.155mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Registers}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave3_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(70)         add  x6, x6, x9                           (6c)         addi x4, x4,  4
(74)         addi x5, x5, -1                           (70)         add  x6, x6, x9
(78)         bne  x5, x0, loop                         (74)         addi x5, x5, -1
(7c) canceled                                          (78)         bne  x5, x0, loop
(68) loop:   lw   x9, 0(x4)                            (7c)         ret  x1
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.7mm}%
\textcolor{cyan}{add}~\hspace{3.155mm}%
addi\hspace{3.155mm}\hspace{.5mm}%
bne~\hspace{.5mm}%
\textcolor{red}{cancel}\hspace{2mm}%
~lw~\hspace{3.155mm}%
addi\hspace{3.155mm}\hspace{.2mm}%
add~\hspace{3.155mm}%
addi\hspace{3.155mm}\hspace{.5mm}%
bne~\hspace{3.155mm}%
ret~\hspace{3.155mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Registers}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave4_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(80) canceled                                          (1c)         addi x5, x0,  3
(10)         sw   x6, 0(x4)                            (20) loop2:  addi x5, x5, -1
(14)         lw   x9, 0(x4)                            (24)         ori  x8, x5, 0xfff
(18)         sub  x8, x9, x4                           (28)         xori x8, x8, 0x555
(1c) stall due to lw-sub                               (2c)         addi x9, x0, -1
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{16.5mm}%
\textcolor{cyan}{cancel}\hspace{1.7mm}%
~sw~\hspace{3.155mm}%
~lw~\,\hspace{3.155mm}%
sub~\hspace{1.3mm}%
\textcolor{magenta}{stall}\hspace{2mm}%
addi\hspace{3.155mm}%
addi\hspace{2.8mm}%
~ori\,\hspace{3.155mm}%
xori\hspace{3.155mm}%
addi

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Registers}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave5_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(30)         andi x10,x9, 0xfff                        (44)         jal  x0, loop2
(34)         or   x4, x10, x9                          (48) cancel
(38)         xor  x8, x10, x9                          (20) loop2:  addi x5, x5, -1
(3c)         and  x7, x10, x4                          (24)         ori  x8, x5, 0xfff
(40)         beq  x5, x0, shift                        (28)         xori x8, x8, 0x555
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.5mm}%
\textcolor{cyan}{andi}\hspace{3.155mm}%
~or~\hspace{3.155mm}%
\,xor~\hspace{3.155mm}%
and~\hspace{3.155mm}%
beq~\hspace{3.155mm}%
jal~\hspace{.7mm}%
\textcolor{red}{cancel}\hspace{1.6mm}%
addi\hspace{3.155mm}%
\,ori\,\hspace{3.155mm}%
xori\hspace{3.155mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Registers}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave6_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(2c)         addi x9, x0, -1                           (40)         beq  x5, x0, shift
(30)         andi x10,x9, 0xfff                        (44)         jal  x0, loop2
(34)         or   x4, x10, x9                          (48) canceled
(38)         xor  x8, x10, x9                          (20) loop2:  addi x5, x5, -1
(3c)         and  x7, x10, x4                          (24)         ori  x8, x5, 0xfff
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.5mm}%
\textcolor{cyan}{addi}\hspace{3.155mm}%
andi\hspace{3.155mm}%
~or~\hspace{3.155mm}%
\,xor~\hspace{3.155mm}%
and~\hspace{3.155mm}%
beq~\hspace{3.155mm}%
jal~\hspace{.6mm}%
\textcolor{red}{cancel}\hspace{1mm}%
addi\hspace{3.155mm}%
~ori~\hspace{3.155mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Registers}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave7_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(28)         xori x8, x8, 0x555                        (3c)         and  x7, x10, x4
(2c)         addi x9, x0, -1                           (40)         beq  x5, x0, shift
(30)         andi x10,x9, 0xfff                        (44) canceled
(34)         or   x4, x10, x9                          (48) shift:  addi x5, x0, -1
(38)         xor  x8, x10, x9                          (4c)         slli x8, x5, 15
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.5mm}%
\textcolor{cyan}{xori}\hspace{3.155mm}%
addi\hspace{3.155mm}%
andi\hspace{3.155mm}%
~or~\hspace{3.155mm}%
\,xor~\hspace{3.155mm}%
and~\hspace{3.1mm}%
beq~\hspace{.5mm}%
\textcolor{red}{cancel}\hspace{1mm}%
addi\hspace{3.155mm}%
slli\hspace{3.155mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Registers}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave8_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(50)         slli x8, x8, 16                           (64) canceled
(54)         srai x8, x8, 16                           (60) finish: jal  x0, finish
(58)         srli x8, x8, 15                           (64) canceled
(5c)         slt  x3, x4, x6                           (60) finish: jal  x0, finish
(60) finish: jal  x0, finish                           (64) canceled
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.5mm}%
\textcolor{cyan}{slli}\hspace{3.155mm}%
srai\hspace{3.155mm}%
srli\hspace{3.155mm}%
\,slt~\hspace{3.155mm}%
jal~\hspace{.75mm}%
\textcolor{red}{cancel}\hspace{2.1mm}%
jal~\hspace{.83mm}%
\textcolor{red}{cancel}\hspace{2.1mm}%
jal~\hspace{.6mm}%
\textcolor{red}{cancel}\hspace{2mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Branch \& Jump}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave01_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(00) main:   lui  x1, 0                                (64) sum:    add  x6, x0, x0
(04)         ori  x4, x1, 80                           (68) loop:   lw   x9, 0(x4)
(08)         addi x5, x0,  4                           (6c)         addi x4, x4,  4
(0c) call:   jal  x1, sum                              (70)         add  x6, x6, x9
(10) canceled                                          (74)         addi x5, x5, -1
\end{code}


\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.7mm}%
\textcolor{cyan}{lui}~\hspace{3.155mm}%
ori~\hspace{3.155mm}%
addi\hspace{3.155mm}%
jal~\hspace{.8mm}%
\textcolor{red}{cancel}\hspace{2mm}%
add~\hspace{2.9mm}%
~lw~\hspace{3.155mm}%
addi\hspace{3.155mm}%
add~\hspace{3.mm}%
addi\hspace{3.155mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Branch \& Jump}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave02_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(78)         bne  x5, x0, loop                         (74)         addi x5, x5, -1
(7c) canceled                                          (78)         bne  x5, x0, loop
(68) loop:   lw   x9, 0(x4)                            (7c) canceled
(6c)         addi x4, x4,  4                           (68) loop:   lw   x9, 0(x4)
(70)         add  x6, x6, x9                           (6c)         addi x4, x4,  4
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.7mm}%
\textcolor{cyan}{bne}~\hspace{.5mm}%
\textcolor{red}{cancel}\hspace{2mm}%
~lw~\hspace{3.155mm}%
addi\hspace{3.155mm}\hspace{.2mm}%
add~\hspace{3.155mm}%
addi\hspace{3.155mm}\hspace{.5mm}%
bne~\hspace{.5mm}%
\textcolor{red}{cancel}\hspace{1.49mm}%
~lw~\hspace{3.155mm}%
addi\hspace{3.155mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Branch \& Jump}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave03_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(70)         add  x6, x6, x9                           (6c)         addi x4, x4,  4
(74)         addi x5, x5, -1                           (70)         add  x6, x6, x9
(78)         bne  x5, x0, loop                         (74)         addi x5, x5, -1
(7c) canceled                                          (78)         bne  x5, x0, loop
(68) loop:   lw   x9, 0(x4)                            (7c)         ret  x1
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.7mm}%
\textcolor{cyan}{add}~\hspace{3.155mm}%
addi\hspace{3.155mm}\hspace{.5mm}%
bne~\hspace{.5mm}%
\textcolor{red}{cancel}\hspace{2mm}%
~lw~\hspace{3.155mm}%
addi\hspace{3.155mm}\hspace{.2mm}%
add~\hspace{3.155mm}%
addi\hspace{3.155mm}\hspace{.5mm}%
bne~\hspace{3.155mm}%
ret~\hspace{3.155mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Branch \& Jump}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave04_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(80) canceled                                          (1c)         addi x5, x0,  3
(10)         sw   x6, 0(x4)                            (20) loop2:  addi x5, x5, -1
(14)         lw   x9, 0(x4)                            (24)         ori  x8, x5, 0xfff
(18)         sub  x8, x9, x4                           (28)         xori x8, x8, 0x555
(1c) stall due to lw-sub                               (2c)         addi x9, x0, -1
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{16.5mm}%
\textcolor{cyan}{cancel}\hspace{1.7mm}%
~sw~\hspace{3.155mm}%
~lw~\,\hspace{3.155mm}%
sub~\hspace{1.3mm}%
\textcolor{magenta}{stall}\hspace{2mm}%
addi\hspace{3.155mm}%
addi\hspace{2.8mm}%
~ori\,\hspace{3.155mm}%
xori\hspace{3.155mm}%
addi

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Branch \& Jump}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave05_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(30)         andi x10,x9, 0xfff                        (44)         jal  x0, loop2
(34)         or   x4, x10, x9                          (48) cancel
(38)         xor  x8, x10, x9                          (20) loop2:  addi x5, x5, -1
(3c)         and  x7, x10, x4                          (24)         ori  x8, x5, 0xfff
(40)         beq  x5, x0, shift                        (28)         xori x8, x8, 0x555
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.5mm}%
\textcolor{cyan}{andi}\hspace{3.155mm}%
~or~\hspace{3.155mm}%
\,xor~\hspace{3.155mm}%
and~\hspace{3.155mm}%
beq~\hspace{3.155mm}%
jal~\hspace{.7mm}%
\textcolor{red}{cancel}\hspace{1.6mm}%
addi\hspace{3.155mm}%
\,ori\,\hspace{3.155mm}%
xori\hspace{3.155mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Branch \& Jump}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave06_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(2c)         addi x9, x0, -1                           (40)         beq  x5, x0, shift
(30)         andi x10,x9, 0xfff                        (44)         jal  x0, loop2
(34)         or   x4, x10, x9                          (48) canceled
(38)         xor  x8, x10, x9                          (20) loop2:  addi x5, x5, -1
(3c)         and  x7, x10, x4                          (24)         ori  x8, x5, 0xfff
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.5mm}%
\textcolor{cyan}{addi}\hspace{3.155mm}%
andi\hspace{3.155mm}%
~or~\hspace{3.155mm}%
\,xor~\hspace{3.155mm}%
and~\hspace{3.155mm}%
beq~\hspace{3.155mm}%
jal~\hspace{.6mm}%
\textcolor{red}{cancel}\hspace{1mm}%
addi\hspace{3.155mm}%
~ori~\hspace{3.155mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Branch \& Jump}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave07_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(28)         xori x8, x8, 0x555                        (3c)         and  x7, x10, x4
(2c)         addi x9, x0, -1                           (40)         beq  x5, x0, shift
(30)         andi x10,x9, 0xfff                        (44) canceled
(34)         or   x4, x10, x9                          (48) shift:  addi x5, x0, -1
(38)         xor  x8, x10, x9                          (4c)         slli x8, x5, 15
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.5mm}%
\textcolor{cyan}{xori}\hspace{3.155mm}%
addi\hspace{3.155mm}%
andi\hspace{3.155mm}%
~or~\hspace{3.155mm}%
\,xor~\hspace{3.155mm}%
and~\hspace{3.1mm}%
beq~\hspace{.5mm}%
\textcolor{red}{cancel}\hspace{1mm}%
addi\hspace{3.155mm}%
slli\hspace{3.155mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション --- Branch \& Jump}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/pl_computer_wave08_.bmp}

\fontsize{8pt}{8}\selectfont
\begin{code}
(50)         slli x8, x8, 16                           (64) canceled
(54)         srai x8, x8, 16                           (60) finish: jal  x0, finish
(58)         srli x8, x8, 15                           (64) canceled
(5c)         slt  x3, x4, x6                           (60) finish: jal  x0, finish
(60) finish: jal  x0, finish                           (64) canceled
\end{code}

\fontsize{10pt}{11}\selectfont
\ttfamily\obeyspaces
\yellow

\vspace{-78.2mm}
\hspace*{18.5mm}%
\textcolor{cyan}{slli}\hspace{3.155mm}%
srai\hspace{3.155mm}%
srli\hspace{3.155mm}%
\,slt~\hspace{3.155mm}%
jal~\hspace{.75mm}%
\textcolor{red}{cancel}\hspace{2.1mm}%
jal~\hspace{.83mm}%
\textcolor{red}{cancel}\hspace{2.1mm}%
jal~\hspace{.6mm}%
\textcolor{red}{cancel}\hspace{2mm}%

\bfseries\cyan
\vspace{-.6mm}
\hspace*{20mm}IF

\vspace{-.6mm}
\hspace*{30mm}ID

\vspace{-.6mm}
\hspace*{40mm}EXE

\vspace{-.6mm}
\hspace*{49.5mm}MEM

\vspace{-.6mm}
\hspace*{60.5mm}WB

\end{frame}
%------------------------------------------------ SLIDE -
\section{RV32M (Mul/Div/Rem) Instructions}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{11pt}{13}\selectfont
\setlength{\tabcolsep}{9pt}
\begin{tabular}{p{1in}p{0.1in}p{0.1in}p{0.1in}p{0.1in}p{0.1in}p{0.8in}p{0.8in}p{1.5in}p{1in}rl}
\cline{1-10}
\multicolumn{4}{|c|}{0000001} &
\multicolumn{2}{c|}{~~~rs2~~~} &
\multicolumn{1}{c|}{~~~rs1~~~} &
\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} && mul \\
\cline{1-10}
\multicolumn{4}{|c|}{0000001} &
\multicolumn{2}{c|}{~~~rs2~~~} &
\multicolumn{1}{c|}{~~~rs1~~~} &
\multicolumn{1}{c|}{001} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} && mulh \\
\cline{1-10}
\multicolumn{4}{|c|}{0000001} &
\multicolumn{2}{c|}{~~~rs2~~~} &
\multicolumn{1}{c|}{~~~rs1~~~} &
\multicolumn{1}{c|}{010} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} && mulhsu \\
\cline{1-10}
\multicolumn{4}{|c|}{0000001} &
\multicolumn{2}{c|}{~~~rs2~~~} &
\multicolumn{1}{c|}{~~~rs1~~~} &
\multicolumn{1}{c|}{011} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} && mulhu \\
\cline{1-10}
\multicolumn{4}{|c|}{0000001} &
\multicolumn{2}{c|}{~~~rs2~~~} &
\multicolumn{1}{c|}{~~~rs1~~~} &
\multicolumn{1}{c|}{100} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} && div \\
\cline{1-10}
\multicolumn{4}{|c|}{0000001} &
\multicolumn{2}{c|}{~~~rs2~~~} &
\multicolumn{1}{c|}{~~~rs1~~~} &
\multicolumn{1}{c|}{101} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} && divu \\
\cline{1-10}
\multicolumn{4}{|c|}{0000001} &
\multicolumn{2}{c|}{~~~rs2~~~} &
\multicolumn{1}{c|}{~~~rs1~~~} &
\multicolumn{1}{c|}{110} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} && rem \\
\cline{1-10}
\multicolumn{4}{|c|}{0000001} &
\multicolumn{2}{c|}{~~~rs2~~~} &
\multicolumn{1}{c|}{~~~rs1~~~} &
\multicolumn{1}{c|}{111} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} && remu \\
\cline{1-10}
\end{tabular}

\vspace{3mm}
\fontsize{8pt}{11}\selectfont
\begin{code}
mul    rd, rs1, rs2   # rd <- rs1 * rs2 (product low, same for signed and unsigned)
mulh   rd, rs1, rs2   # rd <- rs1 * rs2 (product high of   signed *   signed)
mulhsu rd, rs1, rs2   # rd <- rs1 * rs2 (product high of   signed * unsigned)
mulhu  rd, rs1, rs2   # rd <- rs1 * rs2 (product high of unsigned * unsigned)
div    rd, rs1, rs2   # rd <- rs1 / rs2 (  signed)
divu   rd, rs1, rs2   # rd <- rs1 / rs2 (unsigned)
rem    rd, rs1, rs2   # rd <- rs1 % rs2 (  signed)
remu   rd, rs1, rs2   # rd <- rs1 % rs2 (unsigned)
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V RV32M Muse}
\begin{frame}\frametitle{\secname}
\fontsize{13pt}{15}\selectfont
\begin{itemize}
\item ``If both the high and low bits of the same product are
required, then the recommended code sequence is: {\magenta{MULH[[S]U] {\rm rdh,
  rs1, rs2}; MUL {\rm rdl, rs1, rs2}}} (source register specifiers must
be in same order and {\rm rdh} cannot be the same as {\rm rs1} or {\rm
  rs2}).  Microarchitectures can then fuse these into a single
multiply operation instead of performing two separate multiplies.''

\vspace{2mm}
\item ``If both the quotient and remainder
are required from the same division, the recommended code sequence is:
{\magenta{DIV[U] {\rm rdq, rs1, rs2}; REM[U] {\rm rdr, rs1, rs2}}} ({\rm rdq}
cannot be the same as {\rm rs1} or {\rm rs2}).  Microarchitectures can
then fuse these into a single divide operation instead of performing
two separate divides.''
\end{itemize}

\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V Pipelined RV32IM}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=.92\textwidth]{figs/pm_computer_rv32im.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V RV32M Test Program}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{10pt}{14}\selectfont
\begin{code}
.text
# ...
s_x_s:  li     a1, 0x7fffffff # (60,64) a            H = 0xfffffff8
        li     a2, -15        # (68) b               L = 0x8000000f
        mulh   a5,  a1, a2    # (6c) product high
        mul    a4,  a1, a2    # (70) product low, fused with mulh
u_x_u:  li     a1, 0x7fffffff # (74,78) a            H = 0x7ffffffe
        li     a2, -1         # (7c) b               L = 0x80000001
        mulhu  a5,  a1, a2    # (80) product high
        mul    a4,  a1, a2    # (84) product low, fused with mulhu
s_x_u:  li     a1, 0x7fffffff # (88,8c) a            H = 0x7ffffffe
        li     a2, -1         # (90) b               L = 0x80000001
        mulhsu a5,  a1, a2    # (94) product high
        mul    a4,  a1, a2    # (98) product low, fused with mulhsu
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V RV32M Test Program}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{10pt}{14}\selectfont
\begin{code}
sign0:  li     a1, 0x7fffffff # (9c,a0) a            Q = 0x2aaaaaaa
        li     a2,   3        # (a4) b               R = 0x00000001
        div    a5,  a1, a2    # (a8) div signed
        rem    a4,  a1, a2    # (ac) rem signed, fused with div
sign1:  li     a1, 0xfffffff2 # (b0) a               Q = 0xfffffffc
        li     a2,   3        # (b4) b               R = 0xfffffffe
        div    a5,  a1, a2    # (b8) div signed
        rem    a4,  a1, a2    # (bc) rem signed, fused with div
unsign: li     a1, 0xfffffff2 # (c0) a               Q = 0x55555550
        li     a2,   3        # (c4) b               R = 0x00000002
        divu   a5,  a1, a2    # (c8) div unsigned
        remu   a4,  a1, a2    # (cc) rem unsigned, fused with divu
finish: jal    x0, finish     # (d0) dead loop
# ...
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{Simulation Waveform}
\begin{frame}[fragile]\frametitle{\secname}
\vspace{2mm}
\fontsize{13pt}{14}\selectfont
\includegraphics[width=\textwidth]{figs/pm_computer_rv32im_wave_mulh_mul_.bmp}

\tt\obeyspaces
0x7fffffff $\times$ 0xfffffff1 $=$ 0xfffffff8\_8000000f

\red
\     A            B            High     Low

signed $\times$ signed

\vspace{-5mm}

\fontsize{9pt}{14}\selectfont
\vspace{-27.5mm}
\hspace*{55mm}
A

\vspace{-2.6mm}
\hspace*{68.8mm}
B

\vspace{-.59mm}
\hspace*{85mm}
Low

\vspace{-2.52mm}
\hspace*{76.2mm}
High

\yellow
\vspace{-54.7mm}
\hspace*{32.3mm}
mulh\hspace*{1.6mm}mul

\end{frame}
%------------------------------------------------ SLIDE -
\section{Simulation Waveform}
\begin{frame}[fragile]\frametitle{\secname}
\vspace{2mm}
\fontsize{13pt}{14}\selectfont
\includegraphics[width=\textwidth]{figs/pm_computer_rv32im_wave_mulhu_mul_.bmp}

\tt\obeyspaces
0x7fffffff $\times$ 0xffffffff $=$ 0x7ffffffe\_80000001

\red
\     A            B            High     Low

unsigned $\times$ unsigned

\vspace{-5mm}

\fontsize{9pt}{14}\selectfont
\vspace{-27.5mm}
\hspace*{62mm}
A

\vspace{-2.6mm}
\hspace*{75.8mm}
B

\vspace{-.59mm}
\hspace*{92mm}
Low

\vspace{-2.52mm}
\hspace*{83.2mm}
High
\vspace{-2.52mm}
\hspace*{83.2mm}

\yellow
\vspace{-57.1mm}
\hspace*{38.4mm}
mulhu\hspace*{1mm}mul\hspace{27.5mm}mulhsu\hspace*{.7mm}mul

\end{frame}
%------------------------------------------------ SLIDE -
\section{Simulation Waveform}
\begin{frame}[fragile]\frametitle{\secname}
\vspace{2mm}
\fontsize{13pt}{14}\selectfont
\includegraphics[width=\textwidth]{figs/pm_computer_rv32im_wave_div1_rem3_.bmp}

\tt\obeyspaces
0x7fffffff / 3 $=$ 0x2aaaaaaa $\ldots$ 0x00000001

\red
\     A       B         Q            R

signed / signed

\vspace{-5mm}

\fontsize{9pt}{14}\selectfont
\vspace{-27.5mm}
\hspace*{16mm}
A

\vspace{-2.6mm}
\hspace*{85mm}
B

\vspace{-.5mm}
\hspace*{99mm}
R

\vspace{-2.4mm}
\hspace*{92mm}
Q

\yellow
\vspace{-54.9mm}
\hspace*{-.5mm}
div\hspace*{1.6mm}rem\hspace{72.1mm}div\hspace*{2mm}rem

\end{frame}
%------------------------------------------------ SLIDE -
\section{Simulation Waveform}
\begin{frame}[fragile]\frametitle{\secname}
\vspace{2mm}
\fontsize{13pt}{14}\selectfont
\includegraphics[width=\textwidth]{figs/pm_computer_rv32im_wave_div2_rem3_.bmp}

\tt\obeyspaces
0xfffffff2 / 3 $=$ 0xfffffffc $\ldots$ 0xfffffffe

\red
\     A       B         Q            R

signed / signed

\vspace{-5mm}

\fontsize{9pt}{14}\selectfont
\vspace{-27.5mm}
\hspace*{16mm}
A

\vspace{-2.6mm}
\hspace*{18.5mm}
B

\vspace{-.5mm}
\hspace*{90.5mm}
R

\vspace{-2.4mm}
\hspace*{83mm}
Q

\yellow
\vspace{-54.9mm}
\hspace*{74.7mm}
divu\hspace*{.7mm}remu

\end{frame}
%------------------------------------------------ SLIDE -
\section{Simulation Waveform}
\begin{frame}[fragile]\frametitle{\secname}
\vspace{2mm}
\fontsize{13pt}{14}\selectfont
\includegraphics[width=\textwidth]{figs/pm_computer_rv32im_wave_divu_rem3_.bmp}

\tt\obeyspaces
0xfffffff2 / 3 $=$ 0x55555550 $\ldots$ 0x00000002

\red
\     A       B         Q            R

unsigned / unsigned

\vspace{-5mm}

\fontsize{9pt}{14}\selectfont
\vspace{-27.5mm}
\hspace*{16mm}
A

\vspace{-2.6mm}
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B

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R

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Q

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\section{課題 IX (100 点 + 800 点)}
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\item 
%Suppose we have designed three CPUs: Single-cycle CPU, multiple-cycle CPU, and pipelined CPU.
%The clock frequency of the single-cycle CPU is 200MHz; 
%both frequencies of the other two are 1GHz.
%In the multiple-cycle CPU, ``lw'' instruction takes five clock cycles, ``bne'' takes three cycles, and the rest takes four cycles.
%The pipelined CPU uses the techniques of internal forwarding, delayed branch, and pipeline stall.
%Calculate the execution times (ns) when the three CPUs execute the following program.
RISC-V 単一サイクル CPU、マルチサイクル CPU、パイプライン CPU の３つの CPU を設計したとする。
単一サイクル CPU のクロック周波数は 200MHz である。
他の２つの周波数は両方とも 1GHz である。
マルチサイクルCPUでは、「lw」命令は５クロックサイクル、「bne」は３サイクル、残りは４サイクルかかる。
パイプライン CPU は、内部転送、およびパイプラインストールの手法を使用する。
３つの CPU が次のプログラムを実行するときの実行時間（ns）を計算しなさい。

\begin{verbatim}
.text
main:
    lui  x4, %hi(array)     # address of array[0]
    addi x4, x4, %lo(array) # address of array[0]
    add  x2, x0, x0         # sum = 0
    addi x5, x0, 5          # counter = 5
loop:
    lw   x8, 0(x4)          # load array[i] from memory
    add  x2, x2, x8         # sum = sum + array[i]
    addi x4, x4, 4          # address + 4
    addi x5, x5, -1         # counter--
    bne  x5, x0, loop       # if counter != 0, go to loop
    sw   x2, 0(x4)
.data
array: .word 6, 5, -3, 9, 7, 0
.end
\end{verbatim}

さらに、命令の順序を変更して、ロード命令によって引き起こされるパイプラインストールを排除する。そして、実行時間を再計算しなさい。
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\section{課題 IX (100 点 + 800 点)}
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\item オプション（+300 点）: パイプラインCPU RV32I を設計とシミュレーションしなさい。

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RV32I: Integer

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\item オプション（+500 点）: パイプラインCPU RV32IMを設計とシミュレーションしなさい。

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RV32I: Integer

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RV32M: Multiplication/Division (see P53)

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