\documentclass[dvipdfmx,t,serif,mathserif,14pt]{beamer} % t: from top; serif: rmdefault
\usepackage{mybeamer}

\usepackage{mycolor}
\usepackage{contour}

\usepackage{pifont}
\usepackage{alltt}

\newcommand{\PDFTITLE}{コンピュータ構成と設計（８）}
\newcommand{\PDFSUBJECT}{二年生秋学期}
\newcommand{\PDFAUTHOR}{法政大学情報科学部}
\newcommand{\PDFKEYWORDS}{マルチサイクル CPU 設計}
\date{2023 年 11 月 16 日 (木)}

\title{\PDFTITLE} % bottom PDFTITLE
\subtitle{マルチサイクル CPU 設計}
\author[\PDFAUTHOR]{李　亜民} % bottom PDFAUTHOR; titlepage Yamin Li

\hypersetup{
  pdftitle=\PDFTITLE,
  pdfsubject=\PDFSUBJECT,
  pdfauthor=\PDFAUTHOR,
  pdfkeywords=\PDFKEYWORDS
}

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\begin{document}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\everymath={\rm}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{\PDFTITLE}
\begin{frame}
  \titlepage
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{コンピュータとコンピュータシステム}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/CompSys.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{20 RISC-V 命令のまとめ}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{9pt}{11pt}\selectfont
\vspace{-3mm}
\begin{verbatim}
 1. add  rd, rs1, rs2    # rd <- rs1 + rs2
 2. sub  rd, rs1, rs2    # rd <- rs1 - rs2
 3. slt  rd, rs1, rs2    # rd <- rs1 < rs2 (signed)
 4. xor  rd, rs1, rs2    # rd <- rs1 ^ rs2
 5. or   rd, rs1, rs2    # rd <- rs1 | rs2
 6. and  rd, rs1, rs2    # rd <- rs1 & rs2
 7. slli rd, rs1, shamt  # rd <- rs1 << shamt
 8. srli rd, rs1, shamt  # rd <- rs1 >> shamt
 9. srai rd, rs1, shamt  # rd <- rs1 >>>shamt
10. jalr rd, rs1, imm    # rd <- pc+4; pc <- rs1+imm
11. addi rd, rs1, imm    # rd <- rs1 + imm
12. xori rd, rs1, imm    # rd <- rs1 ^ imm
13. ori  rd, rs1, imm    # rd <- rs1 | imm
14. andi rd, rs1, imm    # rd <- rs1 & imm
15. lw   rd,  imm(rs1)   # rd <- memory[rs1+imm]
16. sw   rs2, imm(rs1)   # memory[rs1+imm] <- rs2
17. beq  rs1, rs2, label # if (rs1==rs2) pc <- label
18. bne  rs1, rs2, label # if (rs1!=rs2) pc <- label
19. jal  rd,  label      # rd <- pc+4;   pc <- label
20. lui  rd,  imm        # rd <- imm,000000000000
\end{verbatim}
\end{frame}
%------------------------------------------------ SLIDE -
\section{RV32I Base Instruction Set Encoding}
\begin{frame}\frametitle{\secname}
\fontsize{9pt}{10.6}\selectfont
\begin{tabular}{p{1in}p{0.1in}p{0.1in}p{0.1in}p{0.1in}p{0.1in}p{0.8in}p{0.8in}p{1.5in}p{1in}rl}
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} &1.& add \\
\cline{1-10}
\multicolumn{4}{|c|}{0100000} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} &2.& sub \\
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{010} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} &3.& slt \\
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{100} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} &4.& xor \\
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{110} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} &5.& or \\
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{111} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110011} &6.& and \\
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{\blue shamt} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{001} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &7.& slli \\
\cline{1-10}
\multicolumn{4}{|c|}{0000000} &
\multicolumn{2}{c|}{\blue shamt} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{101} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &8.& srli \\
\cline{1-10}
\multicolumn{4}{|c|}{0100000} &
\multicolumn{2}{c|}{\blue shamt} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{101} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &9.& srai \\
\cline{1-10}
\multicolumn{6}{|c|}{\blue imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{1100111} &10.& jalr \\
\cline{1-10}
\multicolumn{6}{|c|}{\blue imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &11.& addi \\
\cline{1-10}
\multicolumn{6}{|c|}{\blue imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{100} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &12.& xori \\
\cline{1-10}
\multicolumn{6}{|c|}{\blue imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{110} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &13.& ori \\
\cline{1-10}
\multicolumn{6}{|c|}{\blue imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{111} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0010011} &14.& andi \\
\cline{1-10}
\multicolumn{6}{|c|}{\blue imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{010} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0000011} &15.& lw \\
\cline{1-10}
\multicolumn{4}{|c|}{\blue imm[11:5]} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{010} &
\multicolumn{1}{c|}{\blue imm[4:0]} &
\multicolumn{1}{c|}{0100011} &16.& sw \\
\cline{1-10}
\multicolumn{4}{|c|}{\blue imm[12$\vert$10:5]} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{000} &
\multicolumn{1}{c|}{\blue imm[4:1$\vert$11]} &
\multicolumn{1}{c|}{1100011} &17.& beq \\
\cline{1-10}
\multicolumn{4}{|c|}{\blue imm[12$\vert$10:5]} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{001} &
\multicolumn{1}{c|}{\blue imm[4:1$\vert$11]} &
\multicolumn{1}{c|}{1100011} &18.& bne \\
\cline{1-10}
\multicolumn{8}{|c|}{\blue imm[20$\vert$10:1$\vert$11$\vert$19:12]} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{1101111} &19.& jal \\
\cline{1-10}
\multicolumn{8}{|c|}{\blue imm[31:12]} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{0110111} &~~~~20.& lui \\
\cline{1-10}

\end{tabular}
\end{frame}
%------------------------------------------------ SLIDE -
\section{マルチサイクル RISC-V CPU}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/single_vs_multiple_cycle.pdf}

\fontsize{10pt}{10}\selectfont
\renewcommand{\baselinestretch}{1}
%マルチサイクル方式は、命令の各実行{\darkyellow{ステップ}}
%%(命令フェッチ、命令デコード、実行、メモリ･アクセス、結果保存)
%が 1 クロックサイクルを占める

\vspace{3mm}
マルチサイクル方式は、

\begin{itemize}
\item 1 命令の実行を（同程度の処理量の）複数小作業に分割する

\begin{itemize}
\item 各小作業を1クロックサイクルで処理する

\item 1 命令は複数クロックサイクルで実行される
\end{itemize}

\item クロック・サイクル時間を短くする（動作周波数を高くする）
\end{itemize}

\vspace{2mm}
\renewcommand{\arraystretch}{1.0}
\setlength\tabcolsep{2pt}
\begin{tabular}{lll}
IF  & -- & 命令フェッチ ({\blue{I}}nstruction {\blue{F}}etch)\\
ID  & -- & 命令デコード ({\blue{I}}nstruction {\blue{D}}ecode)\\
EXE & -- & 実行 ({\blue{EXE}}cution)\\
MEM & -- & メモリ・アクセス ({\blue{MEM}}ory access)\\
WB  & -- & 書き込み ({\blue{W}}rite {\blue{B}}ack)\\
\end{tabular}

\end{frame}
%------------------------------------------------ SLIDE -
\section{マルチサイクルの実装：状態遷移図}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/9_state_numbers.pdf}

\vspace{2mm}
\resizebox{\textwidth}{!}{
jalr,\,jal,\,beq,\,bne: \textcolor{red}{３}サイクル、
lw: \textcolor{red}{５}サイクル、
それ以外: \textcolor{red}{４}サイクル}
\end{frame}
%------------------------------------------------ SLIDE -
\section{各状態に各命令の操作}
\begin{frame}\frametitle{\secname}
\fontsize{6pt}{10}\selectfont
\setlength\tabcolsep{2pt}
\begin{tabular}{|l||l|l|l|l|l|}\cline{1-5}
\red 命令& \multicolumn{1}{c|}{\red IF} & \multicolumn{1}{c|}{\red ID}& \multicolumn{1}{c|}{\red EAL}& \multicolumn{1}{c|}{\red WAL}\\[-1.5pt]
add  &                         &                         & C $\leftarrow$ A +   B                                                & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
sub  &                         &                         & C $\leftarrow$ A $-$   B                                              & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
slt  &                         &                         & C $\leftarrow$ A $<$   B                                              & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
xor  &                         &                         & C $\leftarrow$ A $\wedge$ B                                           & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
or   &                         &                         & C $\leftarrow$ A \ $|$ \ B                                            & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
and  &                         &                         & C $\leftarrow$ A \ $\&$ \ B                                           & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
slli &                         &                         & C $\leftarrow$ B $<<$ sa                                              & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
srli &                         &                         & C $\leftarrow$ B $>>$ sa                                              & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
srai &                         &                         & C $\leftarrow$ B $>>>$ sa                                             & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
addi &                         & A $\leftarrow$ Reg[rs1] & C $\leftarrow$ A +   imm                                              & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
xori & IR $\leftarrow$ mem[PC] & B $\leftarrow$ Reg[rs2] & C $\leftarrow$ A $\wedge$ imm                                         & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
ori  &                         &                         & C $\leftarrow$ A \ $|$ \ imm                                          & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
andi &                         &                         & C $\leftarrow$ A \ $\&$ \ imm                                         & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
lui  &                         &                         & C $\leftarrow$ imm $<<$ 12                                            & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\\cline{1-1}\cline{4-5}
\red 命令 &                     &                         & \multicolumn{1}{c|}{\red EBR}                                         & \multicolumn{2}{c}{}         \\[-1.5pt]
beq  &                         &                         & if\ (A{\tt{==}}B) PC$\leftarrow$bra; else PC$\leftarrow$PC+4 & \multicolumn{2}{c}{}         \\[-1.5pt]
bne  &                         &                         & if\ (A{\tt{!=}}B) PC$\leftarrow$bra; else PC$\leftarrow$PC+4 & \multicolumn{2}{c}{}         \\[-1.5pt]
jalr &                         &                         &  Reg[rd] $\leftarrow$ PC + 4; PC $\leftarrow$ jalra                   & \multicolumn{2}{c}{}         \\[-1.5pt]
jal  &                         &                         &  Reg[rd] $\leftarrow$ PC + 4; PC $\leftarrow$ jala                    & \multicolumn{2}{c}{}         \\\cline{1-1}\cline{4-6}
\red 命令 &                     &                         & \multicolumn{1}{c|}{\red ELS}&\multicolumn{1}{c|}{\red MLD}           & \multicolumn{1}{c|}{\red WLD}\\[-1.5pt]
lw   &                         &                         &                                                                       & DR $\leftarrow$ mem[C] & Reg[rd] $\leftarrow$ DR; PC $\leftarrow$ PC + 4 \\\cline{1-1}\cline{5-6}
\red 命令 &                     &                         & C $\leftarrow$ A + imm                                                &\multicolumn{1}{c|}{\red MST} \\[-1.5pt]
sw   &                         &                         &                                                                       & mem[C] $\leftarrow$ B; PC $\leftarrow$ PC + 4 \\\cline{1-5}
\end{tabular}
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V マルチサイクルコンピュータ}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer.pdf}

\vspace{2mm}
\color{blue}
CPU $+$ メモリ Mem
\end{frame}
%------------------------------------------------ SLIDE -
\section{CPU 制御ユニットの設計}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{43pt}{55}\selectfont
\begin{center}

\contourlength{1pt} %how thick each copy is
\contournumber{20}  %number of copies
\contour{red}{\textcolor{mycolor187}{制御ユニット}}

(Control Unit)

\vspace{5mm}
\contour{red}{\textcolor{mycolor187}{の設計}}
\end{center}
\end{frame}
%------------------------------------------------ SLIDE -
\section{CPU 制御ユニット}
\begin{frame}[fragile]\frametitle{\secname}
\begin{center}
\includegraphics[scale=1.3]{figs/mc_cu_symbol.pdf}

\vspace{5mm}
赤色の信号は単一サイクルCPUの

\,制御ユニットにはないものである。
\end{center}
\end{frame}
%------------------------------------------------ SLIDE -
\section{制御信号}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{13pt}{13}\selectfont
\begin{itemize}
\item wreg\phantom{l}\phantom{g}
    {\green\begin{itemize}
    \item 1: レジスタ・ファイルに書き込む
    \item 0: レジスタ・ファイルに書き込まない
    \end{itemize}}
\item wmem\phantom{l}\phantom{g}
    {\green\begin{itemize}
    \item 1: メモリに書き込む
    \item 0: メモリに書き込まない
    \end{itemize}}
\item m2reg\phantom{l}\phantom{g}
    {\green\begin{itemize}
    \item 1: メモリから読み出したデータを選択
    \item 0: ALUの出力を選択
    \end{itemize}}
\item bimm\phantom{l}\phantom{g}
    {\green\begin{itemize}
    \item 1: 拡張された即値を選択
    \item 0: レジスタ・ファイル内のデータを選択
    \end{itemize}}
\end{itemize}
\end{frame}
%------------------------------------------------ SLIDE -
\section{制御信号}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{13pt}{13}\selectfont
\begin{itemize}
\item call\phantom{l}\phantom{g}
    {\green\begin{itemize}
    \item 1: PC+4を選択
    \item 0: ALU，または，メモリデータを選択
    \end{itemize}}
\item pcsrc[1:0]\phantom{l}\phantom{g}
    \setlength{\itemsep}{-1.0pt}
    {\green\begin{itemize}
    \item 0 0: PC+4を選択
    \item 0 1: 分岐先アドレスを選択
    \item 1 0: レジスタアドレスを選択
    \item 1 1: ジャンプ先アドレスを選択
    \end{itemize}}
\item alui[1:0]\phantom{l}\phantom{g}
    \setlength{\itemsep}{-1.0pt}
    {\green\begin{itemize}
    \item 0 0: addi, xori, ori, andi, lw 命令の即値を選択
    \item 0 1: slli, srli, srai 命令の shamt を選択
    \item 1 0: sw 命令の即値を選択
    \item 1 1: lui 命令の即値を選択
    \end{itemize}}
\end{itemize}
\end{frame}
%------------------------------------------------ SLIDE -
\section{制御信号}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{13pt}{13}\selectfont
\begin{itemize}
\item aluc[3:0]\phantom{l}\phantom{g}
    \setlength{\itemsep}{-1.0pt}
    {\green\begin{itemize}
 \item\setlength{\tabcolsep}{0pt}\begin{tabular}{p{1.2in}l}x 0 0 0 : ADD &(命令:add, addi, lw, sw)\end{tabular}
 \item\setlength{\tabcolsep}{0pt}\begin{tabular}{p{1.2in}l}x 0 0 1 : SUB &(命令:sub, beq, bne)\end{tabular}
 \item\setlength{\tabcolsep}{0pt}\begin{tabular}{p{1.2in}l}x 0 1 0 : SLT &(命令:slt)\end{tabular}
 \item\setlength{\tabcolsep}{0pt}\begin{tabular}{p{1.2in}l}1 0 1 1 : XOR &(命令:xor, xori)\end{tabular}
 \item\setlength{\tabcolsep}{0pt}\begin{tabular}{p{1.2in}l}x 1 0 0 : OR  &(命令:or, ori)\end{tabular}
 \item\setlength{\tabcolsep}{0pt}\begin{tabular}{p{1.2in}l}x 1 0 1 : AND &(命令:and, andi)\end{tabular}
 \item\setlength{\tabcolsep}{0pt}\begin{tabular}{p{1.2in}l}0 0 1 1 : SLL &(命令:slli)\end{tabular}
 \item\setlength{\tabcolsep}{0pt}\begin{tabular}{p{1.2in}l}0 1 1 1 : SRL &(命令:srli)\end{tabular}
 \item\setlength{\tabcolsep}{0pt}\begin{tabular}{p{1.2in}l}1 1 1 1 : SRA &(命令:srai)\end{tabular}
 \item\setlength{\tabcolsep}{0pt}\begin{tabular}{p{1.2in}l}x 1 1 0 : LUI &(命令:lui)\end{tabular}
    \end{itemize}}
\end{itemize}
\end{frame}
%------------------------------------------------ SLIDE -
\section{制御信号}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{13pt}{13}\selectfont
\begin{itemize}
\color{red}
\setlength{\itemsep}{3mm}
\item wpc\phantom{l}\phantom{g}
    {\green\begin{itemize}
    \color{red}
    \item 1: PC に書き込む
    \item 0: PC に書き込まない
    \end{itemize}}
\item wir\phantom{l}\phantom{g}
    {\green\begin{itemize}
    \color{red}
    \item 1: IR に書き込む
    \item 0: IR に書き込まない
    \end{itemize}}
\item iord\phantom{l}\phantom{g}
    {\green\begin{itemize}
    \color{red}
    \item 1: C\ の値を選択
    \item 0: PC の値を選択
    \end{itemize}}
\item clk: Clock\phantom{l}\phantom{g}
\item clrn: Clear (Active low)\phantom{l}\phantom{g}
\end{itemize}
\end{frame}
%------------------------------------------------ SLIDE -
\section{制御ユニット設計（順序回路）}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_block_diagram.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V マルチサイクルコンピュータ}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer.pdf}

\vspace{2mm}
\color{blue}
CPU $+$ メモリ Mem
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V add, ori: 1. IF 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_if.pdf}

\vspace{2mm}
\color{blue}
IR $\leftarrow$ mem[PC];
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V add, ori: 2. ID 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_id.pdf}

\vspace{2mm}
\color{blue}
B $\leftarrow$ Reg[rs2];

\vspace{-12mm}
A $\leftarrow$ Reg[rs1]; 
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V add, ori: 3. EAL 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_eal.pdf}

\vspace{2mm}
\color{blue}
C $\leftarrow$ A op imm; 

\vspace{-12mm}
C $\leftarrow$ A op B; または
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V add, ori: 4. WAL 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_wal.pdf}

\vspace{2mm}
\color{blue}
PC $\leftarrow$ PC + 4;

\vspace{-12mm}
Reg[rd] $\leftarrow$ C;
\end{frame}
%------------------------------------------------ SLIDE -
% beq, jalr, jal
%------------------------------------------------ SLIDE -
\section{RISC-V beq, jalr, jal: 1. IF 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_if.pdf}

\vspace{2mm}
\color{blue}
IR $\leftarrow$ mem[PC];
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V  beq, jalr, jal: 2. ID 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_id.pdf}

\vspace{2mm}
\color{blue}
B $\leftarrow$ Reg[rs2];

\vspace{-12mm}
A $\leftarrow$ Reg[rs1]; 
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V beq, jalr, jal: 3. EBR 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_ebr.pdf}

\fontsize{11pt}{12}\selectfont
\vspace{-6mm}
\color{blue}
\setlength{\tabcolsep}{2pt}
\begin{tabular}{ll}
jal:  & Reg[rd] $\leftarrow$ PC + 4; PC $\leftarrow$ jala\\
jalr: & Reg[rd] $\leftarrow$ PC + 4; PC $\leftarrow$ jalra\\
beq:  & if\ (A{\tt{==}}B) PC$\leftarrow$bra; else PC$\leftarrow$PC+4\\
bne:  & if\ (A{\tt{!=}}B) PC$\leftarrow$bra; else PC$\leftarrow$PC+4\\
\end{tabular}

\end{frame}
%------------------------------------------------ SLIDE -
% lw
%------------------------------------------------ SLIDE -
\section{RISC-V lw: 1. IF 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_if.pdf}

\vspace{2mm}
\color{blue}
IR $\leftarrow$ mem[PC];
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V lw: 2. ID 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_id.pdf}

\vspace{2mm}
\color{blue}
B $\leftarrow$ Reg[rs2];

\vspace{-12mm}
A $\leftarrow$ Reg[rs1]; 
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V lw: 3. ELS 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_els_lw.pdf}

\vspace{2mm}
\color{blue}
C $\leftarrow$ A + imm; 
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V lw: 4. MLD 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_mld.pdf}

\vspace{2mm}
\color{blue}
DR $\leftarrow$ mem[C]; 
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V lw: 5. WLD 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_wld.pdf}

\vspace{2mm}
\color{blue}
PC $\leftarrow$ PC + 4;

\vspace{-12mm}
Reg[rd] $\leftarrow$ DR;
\end{frame}
%------------------------------------------------ SLIDE -
% sw
%------------------------------------------------ SLIDE -
\section{RISC-V sw: 1. IF 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_if.pdf}

\vspace{2mm}
\color{blue}
IR $\leftarrow$ mem[PC];
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V sw: 2. ID 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_id.pdf}

\vspace{2mm}
\color{blue}
B $\leftarrow$ Reg[rs2];

\vspace{-12mm}
A $\leftarrow$ Reg[rs1]; 
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V sw: 3. ELS 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_els.pdf}

\vspace{2mm}
\color{blue}
C $\leftarrow$ A + imm; 
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V sw: 4. MST 状態}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_cu_mst.pdf}

\vspace{2mm}
\color{blue}
mem[C] $\leftarrow$ B; PC $\leftarrow$ PC + 4;
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V マルチサイクルコンピュータ}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer.pdf}

\vspace{2mm}
\color{blue}
CPU $+$ メモリ Mem
\end{frame}
%------------------------------------------------ SLIDE -
\section{マルチサイクルの実装：状態遷移図}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/9_state_numbers.pdf}

\vspace{2mm}
\resizebox{\textwidth}{!}{
jalr,\,jal,\,beq,\,bne: \textcolor{red}{３}サイクル、
lw: \textcolor{red}{５}サイクル、
それ以外: \textcolor{red}{４}サイクル}
\end{frame}
%------------------------------------------------ SLIDE -
\section{各状態に各命令の操作}
\begin{frame}\frametitle{\secname}
\fontsize{6pt}{10}\selectfont
\setlength\tabcolsep{2pt}
\begin{tabular}{|l||l|l|l|l|l|}\cline{1-5}
\red 命令& \multicolumn{1}{c|}{\red IF} & \multicolumn{1}{c|}{\red ID}& \multicolumn{1}{c|}{\red EAL}& \multicolumn{1}{c|}{\red WAL}\\[-1.5pt]
add  &                         &                         & C $\leftarrow$ A +   B                                                & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
sub  &                         &                         & C $\leftarrow$ A $-$   B                                              & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
slt  &                         &                         & C $\leftarrow$ A $<$   B                                              & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
xor  &                         &                         & C $\leftarrow$ A $\wedge$ B                                           & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
or   &                         &                         & C $\leftarrow$ A \ $|$ \ B                                            & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
and  &                         &                         & C $\leftarrow$ A \ $\&$ \ B                                           & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
slli &                         &                         & C $\leftarrow$ B $<<$ sa                                              & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
srli &                         &                         & C $\leftarrow$ B $>>$ sa                                              & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
srai &                         &                         & C $\leftarrow$ B $>>>$ sa                                             & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
addi &                         & A $\leftarrow$ Reg[rs1] & C $\leftarrow$ A +   imm                                              & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
xori & IR $\leftarrow$ mem[PC] & B $\leftarrow$ Reg[rs2] & C $\leftarrow$ A $\wedge$ imm                                         & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
ori  &                         &                         & C $\leftarrow$ A \ $|$ \ imm                                          & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
andi &                         &                         & C $\leftarrow$ A \ $\&$ \ imm                                         & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\[-1.5pt]
lui  &                         &                         & C $\leftarrow$ imm $<<$ 12                                            & Reg[rd] $\leftarrow$ C; PC $\leftarrow$ PC + 4 \\\cline{1-1}\cline{4-5}
\red 命令 &                     &                         & \multicolumn{1}{c|}{\red EBR}                                         & \multicolumn{2}{c}{}         \\[-1.5pt]
beq  &                         &                         & if\ (A{\tt{==}}B) PC$\leftarrow$bra; else PC$\leftarrow$PC+4 & \multicolumn{2}{c}{}         \\[-1.5pt]
bne  &                         &                         & if\ (A{\tt{!=}}B) PC$\leftarrow$bra; else PC$\leftarrow$PC+4 & \multicolumn{2}{c}{}         \\[-1.5pt]
jalr &                         &                         &  Reg[rd] $\leftarrow$ PC + 4; PC $\leftarrow$ jalra                   & \multicolumn{2}{c}{}         \\[-1.5pt]
jal  &                         &                         &  Reg[rd] $\leftarrow$ PC + 4; PC $\leftarrow$ jala                    & \multicolumn{2}{c}{}         \\\cline{1-1}\cline{4-6}
\red 命令 &                     &                         & \multicolumn{1}{c|}{\red ELS}&\multicolumn{1}{c|}{\red MLD}           & \multicolumn{1}{c|}{\red WLD}\\[-1.5pt]
lw   &                         &                         &                                                                       & DR $\leftarrow$ mem[C] & Reg[rd] $\leftarrow$ DR; PC $\leftarrow$ PC + 4 \\\cline{1-1}\cline{5-6}
\red 命令 &                     &                         & C $\leftarrow$ A + imm                                                &\multicolumn{1}{c|}{\red MST} \\[-1.5pt]
sw   &                         &                         &                                                                       & mem[C] $\leftarrow$ B; PC $\leftarrow$ PC + 4 \\\cline{1-5}
\end{tabular}
\end{frame}
%------------------------------------------------ SLIDE -
\section{制御ユニット設計}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{6pt}{6}\selectfont
\vspace{-2mm}
\begin{code}
module mc_cu (clk,clrn,opcode,func7,func3,z,aluc,alui,pcsrc,m2reg,bimm,call,wreg,wmem,wpc,wir,iord,state);
    input            clk, clrn;                    // clock and reset
    input      [6:0] opcode;                       // opcode
    input      [6:0] func7;                        // func7
    input      [2:0] func3;                        // func3
    input            z;                            // for beq,bne
    output reg [3:0] aluc;                         // alu operation control
    output reg [1:0] alui;                         // 00: addi,...; 01: slli,srli,srai; 10: sw;   11: lui
    output reg [1:0] pcsrc;                        // 00: pc+4;     01: beq,bne;        10: jalr; 11: jal
    output reg       m2reg;                        // instruction is an lw
    output reg       bimm;                         // alu input b is an immediate
    output reg       call;                         // instruction is a jalr or jal
    output reg       wreg;                         // write regfile
    output reg       wmem;                         // memory write enable
    output reg       wpc;                          // write pc
    output reg       wir;                          // write ir
    output reg       iord;                         // select memory address
    output reg [3:0] state;                        // state
    reg        [3:0] next_state;                   // next state
    parameter  [3:0] sif  = 4'b0000,               // IF  state
                     sid  = 4'b0001,               // ID  state
                     seal = 4'b1000,               // EXE Arithmetic Logic state
                     sebr = 4'b0100,               // EXE Branch state
                     sels = 4'b0010,               // EXE Load/Store state
                     smld = 4'b0011,               // MEM Load state
                     smst = 4'b0101,               // MEM Store state
                     swal = 4'b1001,               // WB  Arithmetic Logic state
                     swld = 4'b0110;               // WB  Load state

    // instruction decode
    wire i_lui  = (opcode == 7'b0110111);
    wire i_jal  = ; // add your code here
    wire i_jalr = (opcode == 7'b1100111) & (func3 == 3'b000);
    wire i_beq  = ; // add your code here
    wire i_bne  = ; // add your code here
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{制御ユニット設計}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{6pt}{6}\selectfont
\vspace{-2mm}
\begin{code}
    wire i_lw   = ; // add your code here
    wire i_sw   = ; // add your code here
    wire i_addi = ; // add your code here
    wire i_xori = ; // add your code here
    wire i_ori  = ; // add your code here
    wire i_andi = ; // add your code here
    wire i_slli = (opcode == 7'b0010011) & (func3 == 3'b001) & (func7 == 7'b0000000);
    wire i_srli = ; // add your code here
    wire i_srai = ; // add your code here
    wire i_add  = ; // add your code here
    wire i_sub  = ; // add your code here
    wire i_slt  = ; // add your code here
    wire i_xor  = ; // add your code here
    wire i_or   = ; // add your code here
    wire i_and  = ; // add your code here

    // control signals
    always @* begin                                // default outputs:
        aluc       = 4'bx000;                      // alu operation: add
        alui       = 2'h0;                         // select imm[11:0]
        pcsrc      = 2'h0;                         // select pc+4;
        m2reg      = 0;                            // select reg c
        bimm       = 0;                            // select a;
        call       = 0;                            // neither jalr nor jal
        wreg       = 0;                            // do not write regfile
        wmem       = 0;                            // do not write memory
        wpc        = 0;                            // do not write pc
        wir        = 0;                            // do not write ir
        iord       = 0;                            // select pc as address
        next_state = sif;
        case (state)
            sif: begin                             // IF state --------- IF:
                wir     = 1;                       // write IR
                next_state = sid;                  // next state: ID
            end                                    // 
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{制御ユニット設計}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{6pt}{6}\selectfont
\vspace{-2mm}
\begin{code}
            sid: begin                             // ID state --------- ID:
                case (1)
                    i_beq | i_bne | i_jalr | i_jal: begin // branch or jump instructions
                        next_state = sebr;         // next state: EBR
                    end
                    i_lw | i_sw: begin             // load/store instructions
                        next_state = sels;         // next state: ELS
                    end
                    default: next_state = seal;    // next state: EAL
                endcase
            end
            seal: begin                            // EAL state ------- EAL:
                aluc[0]  = ; // add your code here
                aluc[1]  = ; // add your code here
                aluc[2]  = ; // add your code here
                aluc[3]  = i_xori | i_xor | i_srai;
                bimm     = ; // add your code here
                alui[0]  = ; // add your code here
                alui[1]  = ; // add your code here
                next_state = swal;                 // next state: WAL
            end
            sebr: begin                            // EBR state ------- EBR:
                call       = i_jalr | i_jal;       // save pc+4
                pcsrc[0]   = ; // add your code here
                pcsrc[1]   = ; // add your code here
                aluc       = 4'bx001;              // sub for beq, bne; alu does nothing for jalr, jal
                wpc        = 1;                    // write PC
                wreg       = i_jalr | i_jal;       // save pc+4
                next_state = sif;                  // next state: IF
            end
            sels: begin                            // ELS state ------- ELS:
                alui[1]    = i_sw;                 // alui[1:0] = 10 for sw; 00 for lw
                bimm       = 1;                    // select imm
                if (i_lw) next_state = smld;       // next state: MLD
                else      next_state = smst;       // next state: MST
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{制御ユニット設計}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{6pt}{6}\selectfont
\vspace{-2mm}
\begin{code}
            end
            smld: begin                            // MLD state ------- MLD:
                iord       = 1;                    // memory address = C
                next_state = swld;                 // next state: WLD
            end
            smst: begin                            // MST state ------- MST:
                iord       = 1;                    // memory address = C
                wmem       = 1;                    // write memory
                wpc        = 1;                    // write PC
                next_state = sif;                  // next state: IF
            end
            swld: begin                            // WLD state ------- WLD:
                m2reg      = 1;                    // select memory data
                wreg       = 1;                    // write register file
                wpc        = 1;                    // write PC
                next_state = sif;                  // next state: IF
            end
            swal: begin                            // WAL state ------- WAL:
                wreg       = 1;                    // write register file
                wpc        = 1;                    // write PC
                next_state = sif;                  // next state: IF
            end //----------------------------------------------------- END
            default: begin
                next_state = sif;                  // default state: IF
            end
        endcase
    end
    always @ (posedge clk or negedge clrn) begin
        if (!clrn) begin
            state <= sif;                          // reset state to IF
        end else begin
            state <= next_state;                   // state transition
        end
    end
endmodule
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V マルチサイクルコンピュータ}
\begin{frame}\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer.pdf}

\vspace{2mm}
\color{blue}
CPU $+$ メモリ Mem
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V CPU とメモリの回路}
\begin{frame}[fragile]\frametitle{\secname}
\vspace{2mm}
\resizebox{\textwidth}{!}{{\darkgreen{マルチサイクル RISC-V CPU}} + {\blue{メモリ}}}
\fontsize{10pt}{11}\selectfont

\vspace{12mm}
\includegraphics[width=\textwidth]{figs/mc_cpu+mem.pdf}
\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V mc\_cpu の回路}
\begin{frame}[fragile]\frametitle{\secname}
\vspace{-2mm}
\includegraphics[width=.73\textwidth]{figs/mc_cpu.bmp}

\color{red}
\vspace{-63mm}
\hspace*{7mm}
dffe32 (PC)

\vspace{0mm}
\hspace*{7mm}
pc4

\vspace{5mm}
\hspace*{7mm}
regfile

\vspace{4mm}
\hspace*{7mm}
mux2x32

\vspace{4mm}
\hspace*{7mm}
dff32 (A)

\vspace{2.9mm}
\hspace*{7mm}
dff32 (B)

\vspace{2.9mm}
\hspace*{7mm}
dff32 (C)

%

\vspace{-49mm}
\hspace*{36mm}
mc\_cu

\vspace{6mm}
\hspace*{40mm}
alu

\vspace{2mm}
\hspace*{33mm}
mux2x32

\vspace{1.1mm}
\hspace*{35mm}
imme

\vspace{2mm}
\hspace*{33mm}
mux2x32

\vspace{2mm}
\hspace*{33mm}
mux2x32

%

\vspace{-55mm}
\hspace*{64mm}
dffe32 (IR)

\vspace{11mm}
\hspace*{64mm}
branch\_addr

\vspace{.5mm}
\hspace*{64mm}
jalr\_addr

\vspace{.5mm}
\hspace*{64mm}
jal\_addr

\vspace{3mm}
\hspace*{64mm}
mux4x32

\vspace{4mm}
\hspace*{64mm}
dff32 (DR)

\vspace{2mm}

\fontsize{8pt}{8}\selectfont
\color{blue}
1. File \raisebox{1.4pt}{{\fontsize{7pt}{7}\selectfont$\blacktriangleright$}} Create/Update \raisebox{1.4pt}{{\fontsize{7pt}{7}\selectfont$\blacktriangleright$}} Create Symbol Files for Current File

2. File \raisebox{1.4pt}{{\fontsize{7pt}{7}\selectfont$\blacktriangleright$}} Create/Update \raisebox{1.4pt}{{\fontsize{7pt}{7}\selectfont$\blacktriangleright$}} Create HDL Design File from Current File... Verilog HDL \textcolor{black}{を選択する。}

\end{frame}
%------------------------------------------------ SLIDE -
\section{RISC-V mc\_computer の回路}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=.7\textwidth]{figs/mc_computer.bmp}

\color{red}
\vspace{-17.5mm}
\hspace*{15mm}
mc\_mem
\hspace*{20mm}
mc\_cpu

\vspace{11mm}
\fontsize{8pt}{8}\selectfont
\color{blue}
File \raisebox{1.4pt}{{\fontsize{7pt}{7}\selectfont$\blacktriangleright$}} Create/Update \raisebox{1.4pt}{{\fontsize{7pt}{7}\selectfont$\blacktriangleright$}} Create HDL Design File from Current File... Verilog HDL \textcolor{black}{を選択する。}

\end{frame}
%------------------------------------------------ SLIDE -
\section{メモリ (テスト・プログラムとデータ)}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{5pt}{8}\selectfont
\vspace{-1mm}
\begin{code}
module mc_mem (addr,datain,we,clk,dataout);                // instruction and data memory, ram
    input         clk;                                     // clock
    input         we;                                      // write enable
    input  [31:0] datain;                                  // data in (to memory)
    input  [31:0] addr;                                    // ram address
    output [31:0] dataout;                                 // data out (from memory)
    reg    [31:0] ram [0:63];                              // ram cells: 64 words * 32 bits
    assign dataout = ram[addr[7:2]];                       // use word address to read ram
    always @ (posedge clk)
        if (we) ram[addr[7:2]] = datain;                   // use word address to write ram
    initial begin                                          // initialize memory
        ram[6'h00] = 32'b00000000000000000000000010110111; // (00) main:   lui  x1, 0         # x1 <- 0
        ram[6'h01] = 32'b00001000000000001110001000010011; // (04)         ori  x4, x1, 0x80  # x1 <- 0x80
        ram[6'h02] = 32'b00000000010000000000001010010011; // (08)         addi x5, x0,  4    # x5 <- 4
        ram[6'h03] = 32'b00000101100000000000000011101111; // (0c) call:   jal  x1, sum       # x1 <- 0x10 (return address), call sum
        ram[6'h04] = 32'b00000000011000100010000000100011; // (10)         sw   x6, 0(x4)     # memory[x4+0] <- x6
        ram[6'h05] = 32'b00000000000000100010010010000011; // (14)         lw   x9, 0(x4)     # x6 <- memory[x4+0]
        ram[6'h06] = 32'b01000000010001001000010000110011; // (18)         sub  x8, x9, x4    # x8 <- x9 - x4
        ram[6'h07] = 32'b00000000001100000000001010010011; // (1c)         addi x5, x0,  3    # x5 <- 3
        ram[6'h08] = 32'b11111111111100101000001010010011; // (20) loop2:  addi x5, x5, -1    # x5 <- x5 - 1
        ram[6'h09] = 32'b11111111111100101110010000010011; // (24)         ori  x8, x5, 0xfff # x8 <- x5 | 0xffffffff = 0xffffffff
        ram[6'h0a] = 32'b01010101010101000100010000010011; // (28)         xori x8, x8, 0x555 # x8 <- x8 ^ 0x00000555 = 0xfffffaaa
        ram[6'h0b] = 32'b11111111111100000000010010010011; // (2c)         addi x9, x0, -1    # x9 <- 0xffffffff
        ram[6'h0c] = 32'b11111111111101001111010100010011; // (30)         andi x10,x9, 0xfff # x10<- x9 & 0xffffffff = 0xffffffff
        ram[6'h0d] = 32'b00000000100101010110001000110011; // (34)         or   x4, x10, x9   # x4 <- x10 | x9 = 0xffffffff
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{メモリ (テスト・プログラムとデータ)}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{5pt}{8}\selectfont
\vspace{-1mm}
\begin{code}
        ram[6'h0e] = 32'b00000000100101010100010000110011; // (38)         xor  x8, x10, x9   # x8 <- x10 ^ x9 = 0x00000000
        ram[6'h0f] = 32'b00000000010001010111001110110011; // (3c)         and  x7, x10, x4   # x7 <- x10 & x4 = 0xffffffff
        ram[6'h10] = 32'b00000000000000101000010001100011; // (40)         beq  x5, x0, shift # if x5 = 0, goto shift
        ram[6'h11] = 32'b11111101110111111111000001101111; // (44)         jal  x0, loop2     # jump to loop2
        ram[6'h12] = 32'b11111111111100000000001010010011; // (48) shift:  addi x5, x0, -1    # x5 <- 0xffffffff
        ram[6'h13] = 32'b00000000111100101001010000010011; // (4c)         slli x8, x5, 15    # x8 <- 0xffffffff <<  15 = 0xffff8000
        ram[6'h14] = 32'b00000001000001000001010000010011; // (50)         slli x8, x8, 16    # x8 <- 0xffff8000 <<  16 = 0x80000000
        ram[6'h15] = 32'b01000001000001000101010000010011; // (54)         srai x8, x8, 16    # x8 <- 0x80000000 >>> 16 = 0xffff8000
        ram[6'h16] = 32'b00000000111101000101010000010011; // (58)         srli x8, x8, 15    # x8 <- 0xffff8000 >>  15 = 0x0001ffff
        ram[6'h17] = 32'b00000000011000100010000110110011; // (5c)         slt  x3, x4, x6    # x3 <- 0xffffffff < 0x000002ff = 1
        ram[6'h18] = 32'b00000000000000000000000001101111; // (60) finish: jal  x0, finish    # dead loop
        ram[6'h19] = 32'b00000000000000000000001100110011; // (64) sum:    add  x6, x0, x0    # x6 <- 0 (subroutine entry)
        ram[6'h1a] = 32'b00000000000000100010010010000011; // (68) loop:   lw   x9, 0(x4)     # x9 <- memory[x4+0]
        ram[6'h1b] = 32'b00000000010000100000001000010011; // (6c)         addi x4, x4,  4    # x4 <- x4 + 4 (address+4)
        ram[6'h1c] = 32'b00000000100100110000001100110011; // (70)         add  x6, x6, x9    # x6 <- x6 + x9 (sum)
        ram[6'h1d] = 32'b11111111111100101000001010010011; // (74)         addi x5, x5, -1    # x5 <- x5 - 1 (counter--)
        ram[6'h1e] = 32'b11111110000000101001100011100011; // (78)         bne  x5, x0, loop  # if x5 != 0, goto loop
        ram[6'h1f] = 32'b00000000000000001000000001100111; // (7c)         ret  x1            # return from subroutine
        ram[6'h20] = 32'h000000f2;                         // (80) data[0]
        ram[6'h21] = 32'h0000000e;                         // (84) data[1]
        ram[6'h22] = 32'h00000200;                         // (88) data[2]
        ram[6'h23] = 32'hffffffff;                         // (8c) data[3]
        ram[6'h24] = 32'h00000000;                         // (90) the sum stored by sw instruction
    end
endmodule
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション1}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave01_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(00) main:   lui  x1, 0         # x1 <- 0
(04)         ori  x4, x1, 0x80  # x1 <- 0x80
(08)         addi x5, x0,  4    # x5 <- 4
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID}

\vspace{-17.5mm}
\hspace*{18.7mm}%
\textcolor{yellow}{lui~}\hspace{34mm}%
\textcolor{magenta}{ori~}\hspace{33mm}%
\textcolor{yellow}{addi}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{17.05mm}
\hspace*{55mm}
\fbox{00000000}

\vspace{6.56mm}
\hspace*{96.5mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション2}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave02_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(0c) call:   jal  x1, sum       # x1 <- 0x10, jump to sum
(64) sum:    add  x6, x0, x0    # x6 <- 0
(68) loop:   lw   x9, 0(x4)     # x9 <- memory[x4+0] = 0xf2
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF}

\vspace{-17.5mm}
\hspace*{39mm}%
\textcolor{magenta}{jal~}\hspace{23.5mm}%
\textcolor{yellow}{add~}\hspace{33.5mm}%
\textcolor{magenta}{~lw}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{16.3mm}
\hspace*{66.1mm}
\fbox{\phantom{0000000}}

\vspace{9.83mm}
\hspace*{35.4mm}
\fbox{\phantom{0000000}}

\vspace{0mm}
\hspace*{106mm}
\fbox{00000000}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション3}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave03_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(6c)         addi x4, x4,  4    # x4 <- x4 + 4 = 0x84
(70)         add  x6, x6, x9    # x6 <- x6 + x9 = 0xf2
\end{code}

\ttfamily\obeyspaces
\vspace{-60.0mm}
\hspace*{18.7mm}%
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{MEM}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID}

\vspace{-17.5mm}
\hspace*{59.5mm}%
\textcolor{yellow}{addi}\hspace{34mm}%
\textcolor{magenta}{add}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{27.05mm}
\hspace*{96.5mm}
\fbox{\phantom{0000000}}

\vspace{13.2mm}
\hspace*{55.75mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション4}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave04_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(74)         addi x5, x5, -1    # x5 <- x5 - 1 = 3
(78)         bne  x5, x0, loop  # if x5 != 0, goto loop
(68) loop:   lw   x9, 0(x4)     # x9 <- memory[x4+0] = 0xe
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
%
\textcolor{yellow}{IF}

\vspace{-17.5mm}
\hspace*{39mm}%
\textcolor{yellow}{addi}\hspace{34mm}%
\textcolor{magenta}{bne~}\hspace{23mm}%
\textcolor{yellow}{~lw}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{30.2mm}
\hspace*{76.13mm}
\fbox{\phantom{0000000}}

\vspace{0mm}
\hspace*{35.45mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション5}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave05_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(6c)         addi x4, x4,  4    # x4 <- x4 + 4 = 0x88
(70)         add  x6, x6, x9    # x6 <- x6 + x9 = 0x100
\end{code}

\ttfamily\obeyspaces
\vspace{-60.0mm}
\hspace*{18.7mm}%
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{MEM}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID}

\vspace{-17.5mm}
\hspace*{59.5mm}%
\textcolor{magenta}{addi}\hspace{34mm}%
\textcolor{yellow}{add}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{27.05mm}
\hspace*{96.5mm}
\fbox{\phantom{0000000}}

\vspace{13.2mm}
\hspace*{55.75mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション6}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave06_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(74)         addi x5, x5, -1    # x5 <- x5 - 1 = 2
(78)         bne  x5, x0, loop  # if x5 != 0, goto loop
(68) loop:   lw   x9, 0(x4)     # x9 <- memory[x4+0] = 0x200
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
%
\textcolor{magenta}{IF}

\vspace{-17.5mm}
\hspace*{39mm}%
\textcolor{magenta}{addi}\hspace{34mm}%
\textcolor{yellow}{bne~}\hspace{23mm}%
\textcolor{magenta}{~lw}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{30.2mm}
\hspace*{76.13mm}
\fbox{\phantom{0000000}}

\vspace{0mm}
\hspace*{35.45mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション7}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave07_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(6c)         addi x4, x4,  4    # x4 <- x4 + 4 = 0x8c
(70)         add  x6, x6, x9    # x6 <- x6 + x9 = 0x300
\end{code}

\ttfamily\obeyspaces
\vspace{-60.0mm}
\hspace*{18.7mm}%
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{MEM}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID}

\vspace{-17.5mm}
\hspace*{59.5mm}%
\textcolor{yellow}{addi}\hspace{34mm}%
\textcolor{magenta}{add}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{27.05mm}
\hspace*{96.5mm}
\fbox{\phantom{0000000}}

\vspace{13.2mm}
\hspace*{55.75mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション8}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave08_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(74)         addi x5, x5, -1    # x5 <- x5 - 1 = 1
(78)         bne  x5, x0, loop  # if x5 != 0, goto loop
(68) loop:   lw   x9, 0(x4)     # x9 <- memory[x4+0] = -1
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
%
\textcolor{yellow}{IF}

\vspace{-17.5mm}
\hspace*{39mm}%
\textcolor{yellow}{addi}\hspace{34mm}%
\textcolor{magenta}{bne~}\hspace{23mm}%
\textcolor{yellow}{~lw}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{30.2mm}
\hspace*{76.13mm}
\fbox{\phantom{0000000}}

\vspace{0mm}
\hspace*{35.45mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション9}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave09_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(6c)         addi x4, x4,  4    # x4 <- x4 + 4 = 0x90
(70)         add  x6, x6, x9    # x6 <- x6 + x9 = 0x2ff
\end{code}

\ttfamily\obeyspaces
\vspace{-60.0mm}
\hspace*{18.7mm}%
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{MEM}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID}

\vspace{-17.5mm}
\hspace*{59.5mm}%
\textcolor{magenta}{addi}\hspace{34mm}%
\textcolor{yellow}{add}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{27.05mm}
\hspace*{96.5mm}
\fbox{\phantom{0000000}}

\vspace{13.2mm}
\hspace*{55.75mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション10}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave10_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(74)         addi x5, x5, -1    # x5 <- x5 - 1 = 0
(78)         bne  x5, x0, loop  # if x5 != 0, goto loop
(7c)         ret  x1            # return from sum
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
%
\textcolor{magenta}{IF}

\vspace{-17.5mm}
\hspace*{39mm}%
\textcolor{magenta}{addi}\hspace{34mm}%
\textcolor{yellow}{bne~}\hspace{23mm}%
\textcolor{magenta}{\,ret}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{30.2mm}
\hspace*{76.13mm}
\fbox{\phantom{0000000}}

\vspace{0mm}
\hspace*{35.45mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション11}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave11_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(10)         sw   x6, 0(x4)     # memory[x4+0] <- x6 = 0x2ff
(14)         lw   x9, 0(x4)     # x6 <- memory[x4+0] = 0x2ff
\end{code}

\ttfamily\obeyspaces
\vspace{-60.0mm}
\hspace*{18.7mm}%
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{MEM} \hspace{2.92mm}
%
\textcolor{magenta}{IF} \hspace{3.0mm}
\textcolor{magenta}{ID} \hspace{3.0mm}
\textcolor{magenta}{EXE}\hspace{3.0mm}
\textcolor{magenta}{MEM}

\vspace{-17.5mm}
\hspace*{40mm}%
\textcolor{yellow}{sw}\hspace{37.3mm}%
\textcolor{magenta}{lw}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{.688mm}
\hspace*{35.4mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション12}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave12_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(18)         sub  x8, x9, x4    # x8 <- x9 - x4 = 0x26f
(1c)         addi x5, x0,  3    # x5 <- 3
(20) loop2:  addi x5, x5, -1    # x5 <- x5 - 1 = 2
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF}

\vspace{-17.5mm}
\hspace*{29mm}%
\textcolor{yellow}{sub~}\hspace{33.5mm}%
\textcolor{magenta}{addi}\hspace{33.6mm}%
\textcolor{yellow}{addi}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{30.22mm}
\hspace*{107mm}
\fbox{\phantom{0000000}}

\vspace{6.55mm}
\hspace*{66.1mm}
\fbox{\phantom{0000000}}

\vspace{0mm}
\hspace*{25.15mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション13}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave13_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(24)         ori  x8, x5, 0xfff # x8 <- x5 | 0xffffffff = 0xffffffff
(28)         xori x8, x8, 0x555 # x8 <- x8 ^ 0x00000555 = 0xfffffaaa
\end{code}

\ttfamily\obeyspaces
\vspace{-60.0mm}
\hspace*{18.7mm}%
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}

\vspace{-17.5mm}
\hspace*{50mm}%
\textcolor{magenta}{ori}\hspace{35mm}%
\textcolor{yellow}{xori}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{30.38mm}
\hspace*{45.5mm}
\fbox{\phantom{0000000}}

\vspace{6.55mm}
\hspace*{86.4mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション14}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave14_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(2c)         addi x9, x0, -1    # x9 <- 0xffffffff
(30)         andi x10,x9, 0xfff # x10<- x9 & 0xffffffff = 0xffffffff
(34)         or   x4, x10, x9   # x4 <- x10 | x9 = 0xffffffff
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF}

\vspace{-17.5mm}
\hspace*{28.6mm}%
\textcolor{magenta}{addi}\hspace{34mm}%
\textcolor{yellow}{andi}\hspace{34mm}%
\textcolor{magenta}{\,or}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{40.15mm}
\hspace*{25.35mm}
\fbox{\phantom{0000000}}

\vspace{0mm}
\hspace*{66mm}
\fbox{\phantom{0000000}}

\vspace{0mm}
\hspace*{107mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション15}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave15_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(38)         xor  x8, x10, x9   # x8 <- x10 ^ x9 = 0x00000000
(3c)         and  x7, x10, x4   # x7 <- x10 & x4 = 0xffffffff
\end{code}

\ttfamily\obeyspaces
\vspace{-60.0mm}
\hspace*{18.7mm}%
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}

\vspace{-17.5mm}
\hspace*{50mm}%
\textcolor{yellow}{xor}\hspace{35mm}%
\textcolor{magenta}{and}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{27mm}
\hspace*{45.43mm}
\fbox{\phantom{0000000}}

\vspace{9.9mm}
\hspace*{86.6mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション16}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave16_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(40)         beq  x5, x0, shift # if x5 = 0, goto shift
(44)         jal  x0, loop2     # jump to loop2
(20) loop2:  addi x5, x5, -1    # x5 <- x5 - 1 = 1
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}

\vspace{-17.5mm}
\hspace*{29.6mm}%
\textcolor{yellow}{beq}\hspace{25mm}%
\textcolor{magenta}{jal}\hspace{25mm}%
\textcolor{yellow}{addi}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{36.1mm}
\hspace*{25.35mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション17}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave17_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(24)         ori  x8, x5, 0xfff # x8 <- x5 | 0xffffffff = 0xffffffff
(28)         xori x8, x8, 0x555 # x8 <- x8 ^ 0x00000555 = 0xfffffaaa
(2c)         addi x9, x0, -1    # x9 <- 0xffffffff
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF}

\vspace{-17.5mm}
\hspace*{29.6mm}%
\textcolor{magenta}{ori}\hspace{35mm}%
\textcolor{yellow}{xori}\hspace{33.5mm}%
\textcolor{magenta}{addi}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{30.28mm}
\hspace*{25.35mm}
\fbox{\phantom{0000000}}

\vspace{6.5mm}
\hspace*{66mm}
\fbox{\phantom{0000000}}
\hspace*{28.2mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション18}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave18_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(30)         andi x10,x9, 0xfff # x10<- x9 & 0xffffffff = 0xffffffff
(34)         or   x4, x10, x9   # x4 <- x10 | x9 = 0xffffffff
\end{code}

\ttfamily\obeyspaces
\vspace{-60.0mm}
\hspace*{18.7mm}%
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}

\vspace{-17.5mm}
\hspace*{49mm}%
\textcolor{yellow}{andi}\hspace{35.5mm}%
\textcolor{magenta}{or}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{43.64mm}
\hspace*{45.43mm}
\fbox{ffffffff}

\vspace{-.2mm}
\hspace*{86.6mm}
\fbox{ffffffff}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション19}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave19_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(38)         xor  x8, x10, x9   # x8 <- x10 ^ x9 = 0x00000000
(3c)         and  x7, x10, x4   # x7 <- x10 & x4 = 0xffffffff
(40)         beq  x5, x0, shift # if x5 = 0, goto shift
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF}

\vspace{-17.5mm}
\hspace*{29.6mm}%
\textcolor{yellow}{xor}\hspace{35mm}%
\textcolor{magenta}{and}\hspace{35.5mm}%
\textcolor{yellow}{beq}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{36.1mm}
\hspace*{106mm}
\fbox{ffffffff}

\vspace{-0.1mm}
\hspace*{66.05mm}
\fbox{\phantom{0000000}}

\vspace{-0.1mm}
\hspace*{25.35mm}
\fbox{ffffffff}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション20}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave20_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(44)         jal  x0, loop2     # jump to loop2
(20) loop2:  addi x5, x5, -1    # x5 <- x5 - 1 = 0
(24)         ori  x8, x5, 0xfff # x8 <- x5 | 0xffffffff = 0xffffffff
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF}

\vspace{-17.5mm}
\hspace*{39mm}%
\textcolor{magenta}{jal~}\hspace{23.5mm}%
\textcolor{yellow}{addi}\hspace{33.5mm}%
\textcolor{magenta}{\,ori}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{29.5mm}
\hspace*{107mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション21}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave21_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(28)         xori x8, x8, 0x555 # x8 <- x8 ^ 0x00000555 = 0xfffffaaa
(2c)         addi x9, x0, -1    # x9 <- 0xffffffff
\end{code}

\ttfamily\obeyspaces
\vspace{-60.0mm}
\hspace*{18.7mm}%
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}

\vspace{-17.5mm}
\hspace*{49mm}%
\textcolor{yellow}{xori}\hspace{34mm}%
\textcolor{magenta}{addi}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{40.25mm}
\hspace*{45.5mm}
\fbox{\phantom{0000000}}
\hspace*{28.4mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション22}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave22_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(30)         andi x10,x9, 0xfff # x10<- x9 & 0xffffffff = 0xffffffff
(34)         or   x4, x10, x9   # x4 <- x10 | x9 = 0xffffffff
(38)         xor  x8, x10, x9   # x8 <- x10 ^ x9 = 0x00000000
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF}

\vspace{-17.5mm}
\hspace*{29mm}%
\textcolor{yellow}{andi}\hspace{33.5mm}%
\textcolor{magenta}{~or~}\hspace{33.6mm}%
\textcolor{yellow}{xor}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{27.05mm}
\hspace*{106mm}
\fbox{ffffffff}

\vspace{13.05mm}
\hspace*{25.35mm}
\fbox{ffffffff}

\vspace{-0.2mm}
\hspace*{66.05mm}
\fbox{ffffffff}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション23}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave23_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(3c)         and  x7, x10, x4   # x7 <- x10 & x4 = 0xffffffff
(40)         beq  x5, x0, shift # if x5 = 0, goto shift
\end{code}

\ttfamily\obeyspaces
\vspace{-60.0mm}
\hspace*{18.7mm}%
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}

\vspace{-17.5mm}
\hspace*{50mm}%
\textcolor{magenta}{and}\hspace{35.5mm}%
\textcolor{yellow}{beq}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{36.2mm}
\hspace*{86.6mm}
\fbox{ffffffff}


\vspace{-0.1mm}
\hspace*{45.5mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション24}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave24_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(48) shift:  addi x5, x0, -1    # x5 <- 0xffffffff
(4c)         slli x8, x5, 15    # x8 <- 0xffffffff <<  15 = 0xffff8000
(50)         slli x8, x8, 16    # x8 <- 0xffff8000 <<  16 = 0x80000000
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID}

\vspace{-17.5mm}
\hspace*{18.7mm}%
\textcolor{magenta}{addi}\hspace{33.5mm}%
\textcolor{yellow}{slli}\hspace{33.5mm}%
\textcolor{magenta}{slli}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{30.28mm}
\hspace*{55.75mm}
\fbox{\phantom{0000000}}

\vspace{6.55mm}
\hspace*{96.5mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション25}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave25_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(54)         srai x8, x8, 16    # x8 <- 0x80000000 >>> 16 = 0xffff8000
(58)         srli x8, x8, 15    # x8 <- 0xffff8000 >>  15 = 0x0001ffff
\end{code}

\ttfamily\obeyspaces
\vspace{-60.0mm}
\hspace*{18.7mm}%
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB} \hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
\textcolor{magenta}{WB}

\vspace{-17.5mm}
\hspace*{38.7mm}%
\textcolor{yellow}{srai}\hspace{34mm}%
\textcolor{magenta}{srli}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{40.25mm}
\hspace*{35.45mm}
\fbox{\phantom{0000000}}
\hspace*{28.4mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{シミュレーション26}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/mc_computer_wave26_.bmp}

\fontsize{10pt}{12}\selectfont
\begin{code}
(5c)         slt  x3, x4, x6    # x3 <- 0xffffffff < 0x000002ff = 1
(60) finish: jal  x0, finish    # dead loop
(60) finish: jal  x0, finish    # dead loop
\end{code}

\ttfamily\obeyspaces
\vspace{-64.1mm}
\hspace*{18.7mm}%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}\hspace{3.17mm}
\textcolor{yellow}{WB} \hspace{3.17mm}
%
\textcolor{magenta}{IF} \hspace{3.17mm}
\textcolor{magenta}{ID} \hspace{3.27mm}
\textcolor{magenta}{EXE}\hspace{3.17mm}
%
\textcolor{yellow}{IF} \hspace{3.17mm}
\textcolor{yellow}{ID} \hspace{3.27mm}
\textcolor{yellow}{EXE}

\vspace{-17.5mm}
\hspace*{18.7mm}%
\textcolor{yellow}{slt~}\hspace{33.5mm}%
\textcolor{magenta}{jal~}\hspace{24mm}%
\textcolor{yellow}{jal}

\cyan
\fontsize{7pt}{7}\selectfont
\setlength{\fboxsep}{.5mm}
\setlength{\fboxrule}{.6pt}

\vspace{22.95mm}
\hspace*{55.75mm}
\fbox{\phantom{0000000}}

\end{frame}
%------------------------------------------------ SLIDE -
\section{レジスタファイルの波形を表示する}
\begin{frame}[fragile]\frametitle{\secname}
\includegraphics[width=\textwidth]{figs/ModelSimAddRegisterList.bmp}

\fontsize{10pt}{11}\selectfont

\vspace{6mm}
\raisebox{-1.4pt}{{\fontsize{14pt}{14}\selectfont\textcolor{red}{\ding{172}}}} In the ModelSim main window, check View \raisebox{1.4pt}{{\fontsize{7pt}{7}\selectfont$\blacktriangleright$}} Memory List (w)

\vspace{5mm}
\raisebox{-1.4pt}{{\fontsize{14pt}{14}\selectfont\textcolor{red}{\ding{173}}}} In the ModelSim main window, select the Memory List window

\vspace{5mm}
\raisebox{-1.4pt}{{\fontsize{14pt}{14}\selectfont\textcolor{red}{\ding{174}}}} Drag \textcolor{blue}{/sc\_computer\_tb/cpu/.../register} and drop it to the Wave window

\fontsize{16pt}{16}\selectfont
\color{red}

%\ding{172}--\ding{181} % seriffed fonts
%\ding{192}--\ding{201} % sans-seriffed fonts

\vspace{-69mm}
\hspace*{72.6mm}
\ding{172}

\vspace{28mm}
\hspace*{77.4mm}
\ding{173}

\vspace{-16.7mm}
\hspace*{87mm}
\ding{174}

\vspace{-2mm}
\hspace*{8mm}
\ding{174}
\end{frame}
%------------------------------------------------ SLIDE -
\section{課題 VIII (100 点 + 300 点)}
\begin{frame}[fragile]\frametitle{\secname}
\fontsize{8pt}{11}\selectfont

\vspace{-2mm}
\begin{enumerate}
\item %単一サイクル CPU を設計したとします。
%CPU のクロック周波数は 200MHz です。
%CPU が以下のプログラムを実行するときの実行時間（ns）を計算しなさい。
%Suppose we have designed a single-cycle CPU.
%The clock frequency of the single-cycle CPU is 200MHz.
%Calculate the execution time (ns) when the CPU execute the following program.
%
%Suppose we have designed a single-cycle CPU and a multiple-cycle CPU.
%The clock frequency of the   single-cycle CPU is 200MHz.
%The clock frequency of the multiple-cycle CPU is 1GHz. 
%In the multiple-cycle CPU, ``lw'' instruction takes five clock cycles, ``bne'' takes three cycles, and the rest takes four cycles.
%Calculate the execution times (ns) when the two CPUs execute the following program.
単一サイクル CPU とマルチサイクル CPU を設計したとする。
単一サイクル CPU のクロック周波数は 200MHz である。
マルチサイクル CPU のクロック周波数は 1GHz である。
マルチサイクル CPU では、「lw」命令は５クロックサイクル、「bne」は３サイクル、残りは４サイクルかかる。
２つの CPU が次のプログラムを実行するときの実行時間（ns）を計算しなさい。

\fontsize{8pt}{9}\selectfont
\vspace{1mm}
\begin{verbatim}
.text
main:
    lui  x4, %hi(array)     # address of array[0]
    addi x4, x4, %lo(array) # address of array[0]
    add  x2, x0, x0         # sum = 0
    addi x5, x0, 5          # counter = 5
loop:
    lw   x8, 0(x4)          # load array[i] from memory
    add  x2, x2, x8         # sum = sum + array[i]
    addi x4, x4, 4          # address + 4
    addi x5, x5, -1         # counter--
    bne  x5, x0, loop       # if counter != 0, go to loop
    sw   x2, 0(x4)
.data
array: .word 6, 5, -3, 9, 7, 0
.end
\end{verbatim}

\vspace{1mm}
\item オプション（+300 点）: マルチサイクルコンピュータを設計とシミュレーションしなさい。
\end{enumerate}

\end{frame}
%------------------------------------------------ SLIDE -
\section{dff32.v}
\begin{frame}[fragile]\frametitle{\secname}
\begin{code}
module dff32  (d,clk,clrn,  q);               
    input      [31:0] d;                   
    input             clk, clrn;
    output reg [31:0] q;                   
    always @(negedge clrn or posedge clk)  
        if (!clrn)  q <= 0;                
        else        q <= d;                
endmodule
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
\section{dffe32.v}
\begin{frame}[fragile]\frametitle{\secname}
\begin{code}
module dffe32 (d,clk,clrn,e,q);             
    input      [31:0] d;                   
    input             clk, clrn, e;
    output reg [31:0] q;                   
    always @(negedge clrn or posedge clk)  
        if (!clrn)  q <= 0;                
        else if (e) q <= d;                
endmodule
\end{code}
\end{frame}
%------------------------------------------------ SLIDE -
%------------------------------------------------ SLIDE -
\end{document}
%------------------------------------------------ SLIDE -
